EP1M350 datasheet(51/86 Pages) ALTERA

51 / 86 page

Altera Corporation

Mercury Programmable Logic Device Family Data Sheet

When using the IOE for double data rate outputs, the output register and

OE register are automatically configured to clock two data paths from LEs

on rising clock edges. These register outputs are multiplexed by the clock

to drive the output pin at a

×2 rate. The output register clocks the first bit

out on the clock high time, while the OE register clocks the second bit out

on the clock low time. Figure 28 shows the IOE configured for DDR

output.

Figure 28. IOE Configured for DDR Output

Bidirectional DDR on an I/O pin is possible by using the IOE for DDR

output and using LEs to acquire the double data rate input. Bidirectional

DDR I/O pins support double data rate synchronous DRAM (DDR

SDRAM) at 166 MHz (334 Mbps), which transfer data on a double data

rate bidirectional bus. QDR SRAMs are also supported with DDR I/O

pins on separate read and write ports.

CLRN/PRN

ENA

Chip-Wide Reset

OE Register

CLRN/PRN

ENA

Output Register

Output

Propagation Delay

Drive Strength Control

Open-Drain Output

Slew Control

VCCIO

Optional

PCI Clamp

Programmable

Pull-Up

Associated LAB

Local Interconnect

Two Row

Local Fast

Signals

Six Fast

Global

Signals

Four

Dedicated

Clocks

Bus-Hold

Circuit

EP1M350 Datasheet(PDF) 51 Page - Altera Corporation

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