EP1M350 datasheet(62/86 Pages) ALTERA

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Altera Corporation

Mercury Programmable Logic Device Family Data Sheet

The PLLs in Mercury devices are enabled through the Quartus II software.

External devices are not required to use these features.

Advanced ClockBoost Multiplication & Division

Each Mercury PLL includes circuitry that provides clock synthesis for up

to four outputs (three internal outputs and one external output) using

m/(n

× output divider) scaling. When a PLL is locked, the locked output

clock aligns to the rising edge of the input clock. The closed loop equation

for Figure 31 gives an output frequency fclock0 =(m/(n × k))fIN,

fclock1 =(m/(n × p))fIN, fclock2 =(m/(n × q))fIN, and

fclock_ext =(m/(n × v))fIN or fclock1. These equations allow the

multiplication or division of clocks by a programmable number. The

Quartus II software automatically chooses the appropriate scaling factors

according to the frequency, multiplication, and division values entered.

A single PLL in a Mercury device allows for multiple user-defined

multiplication and division ratios that are not possible even with multiple

delay-locked loops (DLLs). For example, if a frequency scaling factor of

3.75 is needed for a given input clock, a multiplication factor of 15 and a

division factor of 4 can be entered. This advanced multiplication scaling

can be performed with a single PLL, making it unnecessary to cascade

PLL outputs.

External Clock Outputs

Mercury devices have four low-jitter external clocks available for external

clock sources. Other devices on the board can use these outputs as clock

sources.

There are three modes for external clock outputs. Multiplication is

allowed in all external clock output modes.

■

Zero Delay Buffer: The external clock output pin is phase aligned

with the clock input pin for zero delay. Programmable phase shift

and time delay shift are not allowed in this configuration.

Multiplication is allowed with the zero delay buffer mode. The

MegaWizard interface for altclklock should be used to verify

possible clock settings.

■

External Feedback: The external feedback input pin is phase aligned

with clock input pin. By aligning these clocks, you can actively

remove clock delay and skew between devices. Multiplication is

allowed with the external feedback mode. This mode has the same

restrictions as zero delay buffer mode.

EP1M350 Datasheet(PDF) 62 Page - Altera Corporation

EP1M350 Datasheet(HTML) 62 Page - Altera Corporation

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