MC68HC705P9CS datasheet(124/160 Pages) FREESCALE

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Serial Input/Output Port (SIOP)

Technical Data

MC68HC705P9 — Rev. 4.0

124

Serial Input/Output Port (SIOP)

MOTOROLA

Table 10-1. SIOP Timing (V

DD = 5.0 Vdc)

(1)

1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH unless otherwise noted.

Characteristic

Symbol

Min

Max

Unit

Frequency of Operation

Master

Slave

SIOP(M)

fSIOP(S)

fOSC/64

fOSC/8

525

MHz

kHz

Cycle Time

Master

Slave

SCK(M)

tSCK(S)

4.0

—

4.0

1920

tCYC

(2)

2. tCYC = 1 ÷ fOP

Clock (SCK) Low Time (f

OP = 2.1 MHz)

(3)(4)

3. fOSC = crystal frequency; fOP = fOSC ÷ 2 = 2.1 MHz maximum

4. In master mode, the frequency of SCK is fOP ÷ 4.

tSCKL

932

—

SDO Data Valid Time

—

200

SDO Hold Time

tHO

—

SDI Setup Time

100

—

SDI Hold Time

100

—

Table 10-2. SIOP Timing (V

DD = 3.3 Vdc)

(1)

1. VDD = 3.3 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH unless otherwise noted

Characteristic

Symbol

Min

Max

Unit

Frequency of Operation

Master

Slave

SIOP (M)

fSIOP(S)

fOSC/64

fOSC/8

250

MHz

kHz

Cycle Time

Master

Slave

SCK(M)

tSCK(S)

4.0

—

4.0

4000

CYC

(2)

2. tCYC = 1 ÷ fOP

Clock (SCK) Low Time (f

OP = 1.0 MHz)

(3) (4)

3. fOSC = crystal frequency; fOP = fOSC ÷ 2 = 1.0 MHz maximum

4. In master mode, the frequency of SCK is fOP ÷ 4.

tSCKL

1980

—

SDO Data Valid Time

—

400

SDO Hold Time

tHO

—

SDI Setup Time

200

—

SDI Hold Time

200

—

Freescale Semiconductor, Inc.

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