C6416 datasheet(113/134 Pages) TI1

113 / 134 page

SMJ320C6414, SMJ320C6415, SMJ320C6416

FIXEDPOINT DIGITAL SIGNAL PROCESSORS

SGUS050A − JANUARY 2004 − REVISED MARCH 2004

113

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING [C6415 AND C6416 ONLY]

timing requirements for PCLK†‡ (see Figure 47)

NO.

MIN

MAX

UNIT

tc(PCLK)

Cycle time, PCLK

30 (or 8P§)*

tw(PCLKH)

Pulse duration, PCLK high

11*

tw(PCLKL)

Pulse duration, PCLK low

11*

tsr(PCLK)

∆v/∆t slew rate, PCLK

V/ns

*This parameter is not production tested.

† For 3.3-V operation, the reference points for the rise and fall transitions are measured at VILP MAX and VIHP MIN.

‡ P = 1/CPU clock frequency in ns. For example when running parts at 600 MHz, use P = 1.67 ns.

§ Select the parameter value of 30 ns or 8P, whichever is greater.

PCLK

0.4 DVDD V MIN

Peak to Peak for

3.3V signaling

Figure 47. PCLK Timing

timing requirements for PCI reset (see Figure 48)

NO.

MIN

MAX

UNIT

tw(PRST)

Pulse duration, PRST

tsu(PCLKA-PRSTH)

Setup time, PCLK active before PRST high

100*

µs

*This parameter is not production tested.

PRST

PCLK

Figure 48. PCI Reset (PRST) Timing

C6416 Datasheet(PDF) 113 Page - Texas Instruments

C6416 Datasheet(HTML) 113 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL