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C6416 Datasheet(PDF) 116 Page - Texas Instruments

Part # C6416
Description  FIXD-POINT DIGITAL SIGNAL PROCESSORS
PDF  134 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

C6416 Datasheet(HTML) 116 Page - Texas Instruments

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SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
116
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING
timing requirements for McBSP† (see Figure 51)
NO.
MIN
MAX
UNIT
2
tc(CKRX)
Cycle time, CLKR/X
CLKR/X ext
6.67‡*
ns
3
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
0.5tc(CKRX)−1§*
ns
5
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
CLKR int
9
ns
5
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
CLKR ext
1.3
ns
6
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR int
6
ns
6
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR ext
3
ns
7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR int
8
ns
7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR ext
0.9
ns
8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR int
3
ns
8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR ext
3.1
ns
10
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX int
9
ns
10
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX ext
1.3
ns
11
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX int
6
ns
11
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX ext
3
ns
*This parameter is not production tested.
† CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡ Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and ac timing
requirements.
§ This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.



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