C6416 datasheet(117/134 Pages) TI1

117 / 134 page

SMJ320C6414, SMJ320C6415, SMJ320C6416

FIXEDPOINT DIGITAL SIGNAL PROCESSORS

SGUS050A − JANUARY 2004 − REVISED MARCH 2004

117

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)

switching characteristics over recommended operating conditions for McBSP†‡ (see Figure 51)

NO.

PARAMETER

MIN

MAX

UNIT

td(CKSH-CKRXH)

Delay time, CLKS high to CLKR/X high for internal CLKR/X generated

from CLKS input

1.4

tc(CKRX)

Cycle time, CLKR/X

CLKR/X int

6.67§*

tw(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

CLKR/X int

C − 1¶*

C + 1¶*

td(CKRH-FRV)

Delay time, CLKR high to internal FSR valid

CLKR int

−2.1

td(CKXH-FXV)

Delay time, CLKX high to internal FSX valid

CLKX int

−1.7

td(CKXH-FXV)

Delay time, CLKX high to internal FSX valid

CLKX ext

1.7

tdis(CKXH-DXHZ)

Disable time, DX high impedance following last data bit

CLKX int

−3.9*

tdis(CKXH-DXHZ)

Disable time, DX high impedance following last data bit

from CLKX high

CLKX ext

−2.1*

td(CKXH-DXV)

Delay time, CLKX high to DX valid

CLKX int

−3.9 + D1#

4 + D2#

td(CKXH-DXV)

Delay time, CLKX high to DX valid

CLKX ext

−2.1 + D1#

9 + D2#

td(FXH-DXV)

Delay time, FSX high to DX valid

FSX int

−2.3

5.6

td(FXH-DXV)

ONLY applies when in data

delay 0 (XDATDLY = 00b) mode

FSX ext

1.9

*This parameter is not production tested.

† CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

‡ Minimum delay times also represent minimum output hold times.

§ Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing

requirements.

¶ C = H or L

S =

sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)

sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

H =

CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L =

CLKX low pulse width

= (CLKGDV/2) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see ¶ footnote above).

# Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.

if DXENA = 0, then D1 = D2 = 0

if DXENA = 1, then D1 = 4P, D2 = 8P

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