C6416 datasheet(121/134 Pages) TI1

121 / 134 page

SMJ320C6414, SMJ320C6415, SMJ320C6416

FIXEDPOINT DIGITAL SIGNAL PROCESSORS

SGUS050A − JANUARY 2004 − REVISED MARCH 2004

121

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)

timing requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 54)

NO.

MASTER

SLAVE

UNIT

NO.

MIN

MAX

MIN

MAX

UNIT

tsu(DRV-CKXH) Setup time, DR valid before CLKX high

12*

2 − 12P*

th(CKXH-DRV)

Hold time, DR valid after CLKX high

5 + 24P*

*This parameter is not production tested.

† P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.

‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.

switching characteristics over recommended operating conditions for McBSP as SPI Master or

Slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 54)

NO.

PARAMETER

MASTER§

SLAVE

UNIT

NO.

PARAMETER

MIN

MAX

MIN

MAX

UNIT

th(CKXL-FXL)

Hold time, FSX low after CLKX low¶

L − 2*

L + 3*

td(FXL-CKXH)

Delay time, FSX low to CLKX high#

T − 2*

T + 3*

td(CKXL-DXV)

Delay time, CLKX low to DX valid

−2*

12P + 4*

20P + 17*

tdis(CKXL-DXHZ)

Disable time, DX high impedance following last data bit

from CLKX low

−2*

12P + 3*

20P + 17*

td(FXL-DXV)

Delay time, FSX low to DX valid

H − 2*

H + 4*

8P + 2*

16P + 17*

*This parameter is not production tested.

† P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.

‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.

§ S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)

Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T =

CLKX period = (1 + CLKGDV) * S

H =

CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L =

CLKX low pulse width

= (CLKGDV/2) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

¶ FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX

and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP

# FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock

(CLKX).

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

CLKX

FSX

Figure 54. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

C6416 Datasheet(PDF) 121 Page - Texas Instruments

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