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C6416 Datasheet(PDF) 125 Page - Texas Instruments

Part # C6416
Description  FIXD-POINT DIGITAL SIGNAL PROCESSORS
PDF  134 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

C6416 Datasheet(HTML) 125 Page - Texas Instruments

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SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
125
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
UTOPIA SLAVE TIMING [C6415 AND C6416 ONLY] (CONTINUED)
timing requirements for UTOPIA Slave transmit (see Figure 59)
NO.
MIN
MAX
UNIT
2
tsu(UXAV-UXCH)
Setup time, UXADDR valid before UXCLK high
4
ns
3
th(UXCH-UXAV)
Hold time, UXADDR valid after UXCLK high
1
ns
8
tsu(UXENBL-UXCH)
Setup time, UXENB low before UXCLK high
4
ns
9
th(UXCH-UXENBL)
Hold time, UXENB low after UXCLK high
1
ns
switching characteristics over recommended operating conditions for UTOPIA Slave transmit
(see Figure 59)
NO.
PARAMETER
MIN
MAX
UNIT
1
td(UXCH-UXDV)
Delay time, UXCLK high to UXDATA valid
3
12
ns
4
td(UXCH-UXCLAV)
Delay time, UXCLK high to UXCLAV driven active value
3
12
ns
5
td(UXCH-UXCLAVL)
Delay time, UXCLK high to UXCLAV driven inactive low
3*
12*
ns
6
td(UXCH-UXCLAVHZ)
Delay time, UXCLK high to UXCLAV going Hi-Z
9*
18.5*
ns
7
tw(UXCLAVL-UXCLAVHZ)
Pulse duration (low), UXCLAV low to UXCLAV Hi-Z
3*
ns
10
td(UXCH-UXSV)
Delay time, UXCLK high to UXSOC valid
3
12
ns
*This parameter is not production tested.
P47
P48
H1
N
0x1F
N
0x1F
N + 1
0x1F
N
N
10
8
4
3
2
1
UXCLK
UXDATA[7:0]
UXADDR[4:0]
UXCLAV
UXENB
UXSOC
9
P46
P45
0 x1F
The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the UXCLAV and
UXSOC signals).
†
5
6
7
Figure 59. UTOPIA Slave Transmit Timing†



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