C6416 datasheet(124/134 Pages) TI1

124 / 134 page

SMJ320C6414, SMJ320C6415, SMJ320C6416

FIXEDPOINT DIGITAL SIGNAL PROCESSORS

SGUS050A − JANUARY 2004 − REVISED MARCH 2004

124

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

UTOPIA SLAVE TIMING [C6415 AND C6416 ONLY]

timing requirements for UXCLK† (see Figure 57)

NO.

MIN

MAX

UNIT

tc(UXCK)

Cycle time, UXCLK

20*

tw(UXCKH)

Pulse duration, UXCLK high

0.4tc(UXCK)*

0.6tc(UXCK)*

tw(UXCKL)

Pulse duration, UXCLK low

0.4tc(UXCK)*

0.6tc(UXCK)*

tt(UXCK)

Transition time, UXCLK

*This parameter is not production tested.

† The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.

UXCLK

Figure 57. UXCLK Timing

timing requirements for URCLK† (see Figure 58)

NO.

MIN

MAX

UNIT

tc(URCK)

Cycle time, URCLK

20*

tw(URCKH)

Pulse duration, URCLK high

0.4tc(URCK)*

0.6tc(URCK)*

tw(URCKL)

Pulse duration, URCLK low

0.4tc(URCK)*

0.6tc(URCK)*

tt(URCK)

Transition time, URCLK

*This parameter is not production tested.

† The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.

URCLK

Figure 58. URCLK Timing

C6416 Datasheet(PDF) 124 Page - Texas Instruments

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