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C6416 Datasheet(PDF) 126 Page - Texas Instruments

Part # C6416
Description  FIXD-POINT DIGITAL SIGNAL PROCESSORS
PDF  134 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

C6416 Datasheet(HTML) 126 Page - Texas Instruments

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SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
126
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
UTOPIA SLAVE TIMING [C6415 AND C6416 ONLY] (CONTINUED)
timing requirements for UTOPIA Slave receive (see Figure 60)
NO.
MIN
MAX
UNIT
1
tsu(URDV-URCH)
Setup time, URDATA valid before URCLK high
4
ns
2
th(URCH-URDV)
Hold time, URDATA valid after URCLK high
1
ns
3
tsu(URAV-URCH)
Setup time, URADDR valid before URCLK high
4
ns
4
th(URCH-URAV)
Hold time, URADDR valid after URCLK high
1
ns
9
tsu(URENBL-URCH)
Setup time, URENB low before URCLK high
4
ns
10
th(URCH-URENBL)
Hold time, URENB low after URCLK high
1
ns
11
tsu(URSH-URCH)
Setup time, URSOC high before URCLK high
4
ns
12
th(URCH-URSH)
Hold time, URSOC high after URCLK high
1
ns
switching characteristics over recommended operating conditions for UTOPIA Slave receive
(see Figure 60)
NO.
PARAMETER
MIN
MAX
UNIT
5
td(URCH-URCLAV)
Delay time, URCLK high to URCLAV driven active value
3
12
ns
6
td(URCH-URCLAVL)
Delay time, URCLK high to URCLAV driven inactive low
3*
12*
ns
7
td(URCH-URCLAVHZ)
Delay time, URCLK high to URCLAV going Hi-Z
9*
18.5*
ns
8
tw(URCLAVL-URCLAVHZ) Pulse duration (low), URCLAV low to URCLAV Hi-Z
3*
ns
*This parameter is not production tested.
P48
H1
H2
H3
N
0x1F
N+1
0x1F
N+2
0x1F
N
N+1
N+2
12
11
9
10
5
4
3
2
1
URCLK
URDATA[7:0]
URADDR[4:0]
URCLAV
URENB
URSOC
The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the URCLAV and
URSOC signals).
†
8
6
7
Figure 60. UTOPIA Slave Receive Timing†



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