RM0319 datasheet(221/368 Pages) STMICROELECTRONICS

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RM0319

Asynchronous serial ports (UART)

Doc ID 022640 Rev 3

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implemented and are active at all times. Synchronization of control signal is performed on

both directions of data flow.

16.3.10

RS485 interface

In addition to the 7 UART interfaces, SPEAr320S provides an extra UART interface with an

output enable pin (UART_RS485_OE) for an RS485 transceiver. The output status can be

used as valid or invalid, depending on the configuration of the output enable pin.

For example:

UART_RS485_OE = 1’b1 (output is valid)

UART_RS485_OE = 1’b0 (output is invalid)

16.4

Interrupts

Table 63 shows a summary of the 11 maskable interrupts generated within the UART. These

interrupts are combined to form four individual interrupt outputs and one which is the logical

OR of the individual outputs.

The interrupts from UART1 to UART2 are further combined to generate a single interrupt at

the RAS interface. The individual interrupt source can be determined from RAS interrupt

status register.

Any individual interrupt can be enabled or disabled by changing the corresponding mask bit

in the UARTIMSC register. The status of the individual interrupt sources can be read either

from the UARTRIS register for raw status or from the UARTMIS register for the masked

status.

Table 63.

UART interrupt summary together with combined outputs

Name

Source

Combined Outputs

UARTRXINTR

Receive FIFO

UARTRXINTR

UARTINTR

UARTTXINTR

Transmit FIFO

UARTTXINTR

UARTRTINTR

Receive time-out in

Receive FIFO

UARTRTINTR

UARTMSINTR

UARTCTSINTR

UARTDCDINTR

UARTDCSRINTR

UARTOEINTR

Overrun error.

UARTEINTR

UARTBEINTR

Break error

(in reception)

UARTPEINTR

Parity error in the

received character

UARTFEINTR

Framing error in the

received character

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