PM0223 datasheet(19/110 Pages) STMICROELECTRONICS

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PM0223

The STM32L0 Cortex-M0+ Processor

2.1.5

Data types

The processor:

•

Supports the following data types:

–

32-bit words.

–

16-bit halfwords.

–8-bit bytes.

•

Manages all data memory accesses as little-endian or big-endian. Instruction memory

and Private Peripheral Bus (PPB) accesses are always little-endian. See 2.2.1:

Memory regions, types and attributes on page 20 for more information.

2.1.6

The Cortex Microcontroller Software Interface Standard

ARM provides the Cortex Microcontroller Software Interface Standard (CMSIS) for program-

ming STM32L0 Cortex-M0+ microcontrollers. The CMSIS is an integrated part of the device

driver library. For a STM32L0 Cortex-M0+ microcontroller system, CMSIS defines:

•

A common way to:

–

Access peripheral registers.

–

Define exception vectors.

•

The names of:

–

The registers of the core peripherals.

–

The core exception vectors.

•

A device-independent interface for RTOS kernels.

The CMSIS includes address definitions and data structures for the core peripherals in the

STM32L0 Cortex-M0+ processor. It also includes optional interfaces for middleware compo-

nents comprising a TCP/IP stack and a Flash file system.

The CMSIS simplifies software development by enabling the reuse of template code, and

the combination of CMSIS-compliant software components from various middleware ven-

dors. Software vendors can expand the CMSIS to include their peripheral definitions and

access functions for those peripherals.

This document includes the register names defined by the CMSIS, and gives short descrip-

tions of the CMSIS functions that address the processor core and the core peripherals.

Note:

This document uses the register short names defined by the CMSIS. In a few cases these

differ from the architectural short names that might be used in other documents.

The following sections give more information about the CMSIS:

•

2.5.4: Power management programming hints on page 35

•

3.2: Intrinsic functions on page 39

•

4.2.1: Accessing the STM32L0 Cortex-M0+ NVIC registers using CMSIS on page 82

•

NVIC programming hints on page 87

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