M37271MF-252SP datasheet(36/97 Pages) MITSUBISHI

36 / 97 page

MITSUBISHI MICROCOMPUTERS

M37271MF-XXXSP

M37271EF-XXXSP, M37271EFSP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

Fig. 33. Structure of clock run-in register 1

Fig. 36. Structure of clock run-in detect registers 1and 3

Fig. 35. Window setting

Fig. 34. Structure of clock run-in register 3

For the main data slice line, the count value of pulses in the window

is stored in clock run-in register 1 (address 00E616; refer to Figure

33). For the sub-data slice line, the count value of pulses in the window

is stored in clock run-in register 3 (address 020916; refer to Figure

34). When this count value is 4 to 6, it is determined as a clock run-in.

Accordingly, set the count value so that the window may start after

the first pulse of the clock run-in (refer to Figure 35).

The contents to be set in the window register are written at a falling

of the horizontal synchronizing signal. For this reason, even if an

instruction for setting is executed, the contents of the register cannot

be rewritten until a falling of the horizontal synchronizing signal.

For the main data slice line, reference clock is counted in the period

from a falling of the clock pulse set in bits 0 to 2 of the clock run-in

detect register 2 (address 00E916) to the next falling. The count value

is stored in bits 3 to 7 of the clock run-in detect register 1 (address

00E816) (When the count value exceeds “1F16,” “1F16” is held). For

the sub-data slice line, the count value is stored in bits 3 to 7 of the

clock run-in detect register 3 (address 020816). Read out these bits

after the occurence of a data slicer interrupt (refer to (11) Interrupt

Request Generating Circuit).

Figure 36 shows the structure of clock run-in detect registers 1 and

Clock run-in count value of sub-data

slice line

Clock run-in register 3

(CR3 : address 0209 16)

Data latch completion flag for caption data in

sub-data slice line

0: Data is not latched yet

1: Data is latched

Data slice line selection bit for interrupt

request

0: Main data slice line

1: Sub-data slice line

Interrupt mode selection bit

0: Interrupt occurs at end of data slice line

1: Interrupt occurs at completion of caption

data latch

VWhen the count value

in the window is 4 to 6,

this is determined as a

clock run-in.

Horizontal

synchronizing

signal

Composite

video signal

Window

Clock run-in

Start bit data +

16-bit data

Time to be set in the

window register

Time to be set in

the start bit position

Number of reference clocks to

be counted in one clock run-in

pulse period

Clock run-in detect registers 1, 3

( CRD1 : address 00E816)

( CRD3 : address 020816)

Test bits : read-only

Clock run-in count value of

main-data slice line

Clock run-in register 1

(CR1 : address 00E616)

Fix these bits to “01012”

01 0

M37271MF-252SP Datasheet(PDF) 36 Page - Mitsubishi Electric Semiconductor

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