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M37271MF-252SP Datasheet(PDF) 29 Page - Mitsubishi Electric Semiconductor |
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M37271MF-252SP Datasheet(HTML) 29 Page - Mitsubishi Electric Semiconductor |
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29 / 97 page ![]() MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 29 DATA SLICER The M37271MF-XXXSP includes the data slicer function for the closed caption decoder (referred to as the CCD). This function takes out the caption data superimposed in the vertical blanking interval of a composite video signal. A composite video signal which makes the sync chip’s polarity negative is input to the CVIN pin. When the data slicer function is not used, the data slicer circuit can be cut off by setting bit 0 of the data slicer control register 1 (address 00EA16) to “0.” Also, the timing signal generating circuit can be cut off by setting bit 0 of data slicer control register 2 (address 00EB16) to “0.” These settings can realize the low-power dissipation. Fig. 22. Data slicer block diagram 10 0 00 00 10 1 Composite video signal Hundred of kiloohms to 1 M Ω Sync pulse counter register (address 020F16) Clock run-in register 2 (address 00E716) Data slicer control register 2 (address 00EB16) Data slicer control register 1 (address 00EA16) Window register (address 00E216) Clock run-in register 1 (address 00E616) Caption position register (address 00E016) Start bit position register (address 00E116) Clock run-in detect register 1 (address 00E816) Clock run-in detect register 2 (address 00E916) Interrupt request generating circuit Data slicer interrupt request Synchronizing signal counter Synchronizing separation circuit Sync slice circuit Clamping circuit Low-pass filter Timing signal generating circuit Clock run-in determination circuit Data slice line specification circuit Start bit detecting circuit Data clock generating circuit 16-bit shift register Data register 1 (address 00E416) Data register 2 (address 00E516) Sync slice register 3 (address 00E316) Data bus Comparator 0 1 0 111 00 0 00 0 00 0 10 1 0.1 µF 470 Ω 560 pF CVIN 1 µF 1 k Ω 200 pF 15 k Ω HSYNC HLF RVCO + – Reference voltage generating circuit VHOLD 1000 pF high-order low-order Data slicer ON/OFF Data register 4 (address 00ED16) Data register 3 (address 00EC16) Data slicer control register 3 (address 021016) Clock run-in detect register 3 (address 020816) Clock run-in register 3 (address 020916) External circuit Note: Make the length of wiring which is connected to VHOLD, HLF, RVCO and CVIN pin as short as possible so that a leakage current may not be generated when mounting a resistor or a capacitor on each pin. |
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