M37271MF-252SP datasheet(53/97 Pages) MITSUBISHI

53 / 97 page

MITSUBISHI MICROCOMPUTERS

M37271MF-XXXSP

M37271EF-XXXSP, M37271EFSP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

The display position in the vertical direction is determined by count-

ing the horizontal sync signal (HSYNC). At this time, it starts to count

the rising edge (falling edge) of HSYNC signal from after about 1 ma-

chine cycle of rising edge (falling edge) of VSYNC signal. So interval

from rising edge (falling edge) of VSYNC signal to rising edge (falling

edge) of HSYNC signal needs enough time (2 machine cycles or more)

for avoiding jitter. The polarity of HSYNC and VSYNC signals can se-

lect with the I/O polarity control register (address 021716). For de-

tails, refer to (15) OSD Output Pin Control.

Note: When bits 0 and 1 of the I/O polarity control register (address

021716) are set to “1” (negative polarity), the vertical position

is determined by counting falling edge of HSYNC signal after

rising edge of VSYNC control signal in the microcomputer (re-

fer to Figure 57).

Fig. 57. Supplement explanation for display position

The vertical position for each block can be set in 1024 steps (where

each step is 1TH (TH: HSYNC cycle)) as values “0016” to “FF16” in

vertical position register 1i (i = 1 to 16) (addresses 022016 to 022F16)

and values “0016” to “FF16” in the vertical position register 2i (i = 1 to

16) (addresses 023016 to 023F16). The structure of the vertical posi-

tion registers is shown in Figure 58.

Fig. 58. Structure of vertical position registers

The horizontal position is common to all blocks, and can be set in

256 steps (where 1 step is 4TC, TC being the oscillating cycle for

display) as values “0016” to “FF16” in bits 0 to 7 of the horizontal

position register (address 00CF16). The structure of the horizontal

position register is shown in Figure 59.

Fig. 59. Structure of horizontal position register

When bits 0 and 1 of the I/O polarity control register

(address 021716) are set to “1” (negative polarity)

VSYNC signal input

VSYNC control

signal in

microcomputer

0.25 to 0.50 [

µs]

( at f(XIN) = 8MHz)

Period of counting

HSYNC signal

(Note 1)

HSYNC

signal input

Not count

12345

Notes 1 : Do not generate falling edge of H SYNC signal near rising edge of

VSYNC control signal in microcomputer to avoid jitter.

2 : The pulse width of VSYNC and HSYNC needs 8 machine cycles or

more.

Vertical position register 1i

(i = 1 to 16)

(VP1i : addresses 022016 to 022F16)

Control bits of vertical display

start positions (Note)

Vertical display start positions (low-order 8 bits)

TH!(setting value of low-order 2 bits of VP2i !16

+setting value of low-order 4 bits of VP1i !16

+setting value of low-order 4 bits of VP1i !16 )

Note : Set values except “00 16” and “0116” to VP1i when VP2i is “00 16.”

Vertical position register 2i

(i = 1 to 16)

(VP2i : addresses 023016 to 023F16)

Control bits of vertical display

start positions (Note)

Vertical display start positions (high-order 2 bits)

TH!(setting value of low-order 2 bits of VP2i !16

+setting value of low-order 4 bits of VP1i !16

+setting value of low-order 4 bits of VP1i !16 )

Note : The setting value synchronizes with a rising (falling) of the V SYNC.

Horizontal position register

(HP : address 00CF16)

Control bits of horizontal display

start positions

Horizontal display start positions

4TOSC!(setting value of high-order 4 bits !16

+setting value of low-order 4 bits !16 )

M37271MF-252SP Datasheet(PDF) 53 Page - Mitsubishi Electric Semiconductor

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