M37271MF-252SP datasheet(31/97 Pages) MITSUBISHI

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MITSUBISHI MICROCOMPUTERS

M37271MF-XXXSP

M37271EF-XXXSP, M37271EFSP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

(1) Clamping Circuit and Low-pass Filter

This filter attenuates the noise of the composite video signal input

from the CVIN pin. The CVIN pin to which composite video signal is

input requires a capacitor (0.1

µF) coupling outside. Pull down the

CVIN pin with a resistor of hundreds of kiloohms to 1 M . In addition,

we recommend to install externally a simple low-pass filter using a

resistor and a capacitor at the CVIN pin (refer to Figure 22).

(2) Sync Slice Circuit

This circuit takes out a composite sync signal from the output signal

of the low-pass filter. Figure 24 shows the structure of the sync slice

(3) Synchronizing Signal Separation Circuit

This circuit separates a horizontal synchronizing signal and a vertical

synchronizing signal from the composite sync signal taken out in the

sync slice circuit.

1Horizontal synchronizing signal (Hsep)

A one-shot horizontal synchronizing signal Hsep is generated at

the falling edge of the composite sync signal.

2 Vertical synchronizing signal (Vsep)

As a Vsep signal generating method, it is possible to select one of

the following 2 methods by using bit 7 of the sync slice register

(address 00E316).

•Method 1

The “L” level width of the composite sync signal is

measured. If this width exceeds a certain time, a Vsep

signal is generated in synchronization with the rising

of the timing signal immediately after this “L” level.

•Method 2

The “L” level width of the composite sync signal is

measured. If this width exceeds a certain time, it is

detected whether a falling of the composite sync

signal exits or not in the “L” level period of the timing

signal immediately after this “L” level. If a falling exists,

a Vsep signal is generated in synchronization with

the rising of the timing signal (refer to Figure 25).

Figure 25 shows a Vsep generating timing. The timing signal shown

in the figure is generated from the reference clock which the timing

generating circuit outputs.

Reading bit 5 of data slicer control register 2 permits determinating

the shape of the V-pulse portion of the composite sync signal. As

shown in Figure 26, when the A level matches the B level, this bit is

“0.” In the case of a mismatch, the bit is “1.”

For the pins RVCO and the HLF, connect a resistor and a capacitor

as shown in Figure 22. Make the length of wiring which is connected

to these pins as short as possible so that a leakage current may not

be generated.

Note: It takes a few tens of milliseconds until the reference clock

becomes stable after the data slicer and the timing signal

generating circuit are started. In this period, various timing

signals, Hsep signals and Vsep signals become unstable. For

this reason, take stabilization time into consideration when

programming.

Fig. 24. Structure of sync slice register

Fig. 25. Vsep generating timing (method 2)

Composite

sync signal

Timing

signal

Vsep signal

Measure “L” period

A Vsep signal is generated at a rising of the timing signal

immediately after the “L” level width of the composite

sync signal exceeds a certain time.

Sync slice register

(SSL : address 00E316)

Fix these bits to “00001012”

Vertical synchronizing

signal (Vsep) generating

method selection bit

0 : Method 1

1 : Method 2

M37271MF-252SP Datasheet(PDF) 31 Page - Mitsubishi Electric Semiconductor

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