CP3SP33SMSSLASHNOPB datasheet(178/407 Pages) TI1

178 / 407 page

1 to 8 Time Quanta

2 to 16 Time Quanta

4 to 25 TIme Quanta

SAMPLE

POINT

TRANSMISSION

POINT

INTERNAL

TIME QUANTA

CLOCK

ONE TIME QUANTUM

1 TIme

Quantum

TIME SEGMENT 1 (TSEG1)

TIME SEGMENT 2 (TSEG2)

A = synchronization segment (Sync)

DS028

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

22.2.6 Bit Time Logic

In the Bit Time Logic (BTL), the CAN bus speed and the Synchronization Jump Width can be configured

by software. The CAN module divides a nominal bit time into three time segments: synchronization

segment, time segment 1 (TSEG1), and time segment 2 (TSEG2). Figure 22-11 shows the various

elements of a CAN bit time.

22.2.6.1 CAN Bit Time

The number of time quanta in a CAN bit (CAN Bit Time) ranges between 4 and 25. The sample point is

positioned between TSEG1 and TSEG2 and the transmission point is positioned at the end of TSEG2.

Figure 22-11. Bit Timing

TSEG1 includes the propagation segment and the phase segment 1 as specified in the CAN specification

2.0B. The length of the time segment 1 in time quanta (tq) is defined by the TSEG1[3:0] bits.

TSEG2 represents the phase segment 2 as specified in the CAN specification 2.0B. The length of time

segment 2 in time quanta (tq) is defined by the TSEG2[3:0] bits.

The Synchronization Jump Width (SJW) defines the maximum number of time quanta (tq) by which a

received CAN bit can be shortened or lengthened in order to achieve resynchronization on “recessive” to

“dominant” data transitions on the bus. In the CAN implementation, the SJW must be configured less or

equal to TSEG1 or TSEG2, whichever is smaller.

22.2.6.2 Synchronization

The Synchronization Jump Width (SJW) defines the maximum number of time quanta (tq) by which a

received CAN bit can be shortened or lengthened in order to achieve re-synchronization on “recessive” to

“dominant” data trans tions on the bus. In the CAN implementation, the SJW must be configured less or

equal to TSEG1 or TSEG2, whichever is smaller.

However, two CAN nodes never operate at exactly the same clock rate, and the bus signal may deviate

from the ideal waveform due to the physical conditions of the network (bus length and load). To

compensate for the various delays within a network, the sample point can be positioned by programming

the length of TSEG1 and TSEG2 (see Figure 22-11).

In addition, two types of synchronization are supported. The BTL logic compares the incoming edge of a

CAN bit with the internal bit timing. The internal bit timing can be adapted by either hard or soft

synchronization (re-synchronization).

Hard synchronization is performed at the beginning of a new frame with the falling edge on the bus while

the bus is idle. This is interpreted as the SOF. It restarts the internal logic.

178

Dual CAN Interfaces

Submit Documentation Feedback

Product Folder Links :CP3SP33

CP3SP33SMS/NOPB Datasheet(PDF) 178 Page - Texas Instruments

CP3SP33SMS/NOPB Datasheet(HTML) 178 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL