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XM014034B Datasheet(PDF) 13 Page - Xmos Ltd.

Part # XM014034B
Description  XCore xcore.ai Microcontroller IC 32-Bit 16-Core 2400MIPs 8KB (8K x 8) OTP 60-QFN (7x7)
PDF  83 Pages
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Manufacturer  XMOS [Xmos Ltd.]
Direct Link  https://www.xmos.ai/
Logo XMOS - Xmos Ltd.

XM014034B Datasheet(HTML) 13 Page - Xmos Ltd.

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XU6--QF6A Datasheet
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clock block
port counter
1-bit port
100MHz
reference
clock
divider
Figure :
Clock block
diagram
On reset, each port is connected to clock block , which runs from the xCORE Tile refer-
ence clock.
6.
Channels and Channel Ends
Logical cores communicate using point-to-point connections, formed between two chan-
nel ends. A channel-end is a resource on an xCORE tile, that is allocated by the program.
Each channel-end has a unique system-wide identier that comprises a unique number
and their tile identier. Data is transmitted to a channel-end by an output-instruction;
and the other side executes an input-instruction. Data can be passed synchronously or
asynchronously between the channel ends.
6.6 xCONNECT Switch and Links
XMOS devices provide a scalable architecture, where multiple xCORE devices can be con-
nected together to form one system. Each xCORE device has an xCONNECT interconnect
that provides a communication infrastructure for all tasks that run on the various xCORE
tiles on the system.
The interconnect relies on a collection of switches and XMOS links. Each xCORE device
has an on-chip switch that can set up circuits or route data. The switches are connected
by xConnect Links. An XMOS link provides a physical connection between two switches.
The switch has a routing algorithm that supports many different topologies, including
lines, meshes, trees, and hypercubes.
The links operate in either wires per direction or wires per direction mode, depending
on the amount of bandwidth required. Circuit switched, streaming and packet switched
data can both be supported efciently. Streams provide the fastest possible data rates
between xCORE Tiles, but each stream requires a single link to be reserved between
switches on two tiles. All packet communications can be multiplexed onto a single link.
Information on the supported routing topologies that can be used to connect multiple
devices together can be found in the xCONNECT Architecture guide.



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