XM014034B datasheet(38/83 Pages) XMOS

38 / 83 page

XU6--QF6A Datasheet

Appendices

Conguration of the XU6--QF6A

The device is congured through banks of registers, as shown in Figure

X0Dxx

I/O pins

xTIME

scheduler

Hardware response ports

core

PLL

app

PLL

JTAG

X1Dxx

I/O pins

xTIME

scheduler

Hardware response ports

Internal

SRAM

OTP

ALU (FP + int)

Vector unit

Internal

SRAM

OTP

ALU (FP + int)

Vector unit

xCORE "logical" core

Figure

Registers

The following communication sequences specify how to access those registers. Any

messages transmitted contain the most signicant

bits of the channel-end to which

a response is to be sent. This comprises the node-identier and the channel number

within the node. if no response is required on a write operation, supply

-bits with the

last 8-bits set, which suppresses the reply message. Any multi-byte data is sent most

signicant byte rst.

Registers are addressed by a number, for each register a symbolic constant is dened in

the xs1.h include le which has one of the following three names:

XS1_PS_NAME for processor status registers.

XS1_PSWITCH_NAME_NUM for tile conguration registers.

XS1_SSWITCH_NAME_NUM for node conguration registers.

Each register typically comprises a set of bit-elds that control individual functions. These

bitelds are specied in the tables in subsequent appendices. Macros are dened in the

xs1.h include le which perform the following support functions:

XS1_NAME(x) The value of the biteld extracted from a word x.

x = XS1_NAME_SET(x, v) Setting the biteld in a word x to the value v.

Registers and bit-elds have permissions as follows:

read-only

read and write

XM014034B Datasheet(PDF) 38 Page - Xmos Ltd.

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