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XM014034B Datasheet(PDF) 49 Page - Xmos Ltd.

Part # XM014034B
Description  XCore xcore.ai Microcontroller IC 32-Bit 16-Core 2400MIPs 8KB (8K x 8) OTP 60-QFN (7x7)
PDF  83 Pages
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Manufacturer  XMOS [Xmos Ltd.]
Direct Link  https://www.xmos.ai/
Logo XMOS - Xmos Ltd.

XM014034B Datasheet(HTML) 49 Page - Xmos Ltd.

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XU6--QF6A Datasheet
B.
Data watchpoint address
DBG_DWATCH_ADDR1 0x50 .. 0x53
This set of registers contains the rst address for the four data watchpoints. Condition
A
of a watchpoint is met if the effective address of an instruction is greater than or equal
to the value in this register.
The CTRL register for the watchpoint will dictate whether the watchpoint triggers on
stores only or on loads and stores, and whether it requires either condition A or B, or
both A and B.
Bits
Perm
Init
Description
Identier
:
DRW
Value.
ALL_BITS
x
.. x:
Data
watchpoint
address
B.
Data watchpoint address
DBG_DWATCH_ADDR2 0x60 .. 0x63
This set of registers contains the second address for the four data watchpoints. Con-
dition B of a watchpoint is met if the effective address of an instruction is less than or
equal to the value in this register.
The CTRL register for the watchpoint will dictate whether the watchpoint triggers on
stores only or on loads and stores, and whether it requires either condition A or B, or
both A and B.
Bits
Perm
Init
Description
Identier
:
DRW
Value.
ALL_BITS
x6 .. x6:
Data
watchpoint
address
B.
Data breakpoint control register
DBG_DWATCH_CTRL 0x70 .. 0x73
This set of registers controls each of the four data watchpoints.
Bits
Perm
Init
Description
Identier
:
RO
-
Reserved
:6
DRW
A bit for each thread in the machine allowing the breakpoint to be en-
abled individually for each thread.
BRK_THREADS
:
RO
-
Reserved
DRW
When the breakpoints will be be triggered on loads.
BRK_LOAD
DRW
Determines the break condition: = A AND B, = A OR B. DBRK_CONDITION
DRW
When the breakpoint is enabled.
BRK_ENABLE
x
.. x:
Data
breakpoint
control
register
8



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