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XM014034B Datasheet(PDF) 41 Page - Xmos Ltd. |
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XM014034B Datasheet(HTML) 41 Page - Xmos Ltd. |
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41 / 83 page ![]() XU6--QF6A Datasheet B Processor Status Conguration The processor status control registers can be accessed directly by the processor using processor status reads and writes (use getps(reg) and setps(reg,value) for reads and writes). The identiers for the registers needs a prex “XS1_PS_” and a postx “_NUM”, and are declared in “xs1.h” Number Perm Description Register identier x RW RAM base address RAM_BASE x RW Vector base address VECTOR_BASE x RW xCORE Tile control XCORE_CTRL0 x RO xCORE Tile boot status BOOT_CONFIG x RW Security conguration SECURITY_CONFIG x6 RW Ring Oscillator Control RING_OSC_CTRL x RO Ring Oscillator Value RING_OSC_DATA0 x8 RO Ring Oscillator Value RING_OSC_DATA1 x RO Ring Oscillator Value RING_OSC_DATA2 xA RO Ring Oscillator Value RING_OSC_DATA3 xC RO RAM size RAM_SIZE x DRW Debug SSR DBG_SSR x DRW Debug SPC DBG_SPC x DRW Debug SSP DBG_SSP x DRW DGETREG operand DBG_T_NUM x DRW DGETREG operand DBG_T_REG x DRW Debug interrupt type DBG_TYPE x6 DRW Debug interrupt data DBG_DATA x8 DRW Debug core control DBG_RUN_CTRL x .. x DRW Debug scratch DBG_SCRATCH x .. x DRW Instruction breakpoint address DBG_IBREAK_ADDR x .. x DRW Instruction breakpoint control DBG_IBREAK_CTRL x .. x DRW Data watchpoint address DBG_DWATCH_ADDR1 x6 .. x6 DRW Data watchpoint address DBG_DWATCH_ADDR2 x .. x DRW Data breakpoint control register DBG_DWATCH_CTRL Figure : Summary |
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