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XM014034B Datasheet(PDF) 61 Page - Xmos Ltd. |
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XM014034B Datasheet(HTML) 61 Page - Xmos Ltd. |
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61 / 83 page  XU6--QF6A Datasheet Bits Perm Init Description Identier RW = SSCTL registers have write access. = SSCTL registers can not be written to. SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE : RO - Reserved 8 RW = PLL_CTL_REG has write access. = PLL_CTL_REG can not be writ- ten to. SS_NODE_CONFIG_DISABLE_PLL_CTL_REG : RO - Reserved RW = -byte headers, = -byte headers (reset as ). SS_NODE_CONFIG_HEADERS x: Switch conguration D. Switch node identier NODE_ID 0x05 This register contains the node identier. Bits Perm Init Description Identier :6 RO - Reserved : RW The unique ID of this node. SS_NODE_ID_ID x: Switch node identier D. PLL settings PLL_CTL 0x06 An on-chip PLL multiplies the input clock up to a higher frequency clock, used to clock the I/O, processor, and switch, see Oscillator. Note: a write to this register will cause the tile to be reset. Bits Perm Init Description Identier RW If set to , the chip will not be reset SS_PLL_CTL_NRESET RW If set to , the chip will not wait for the PLL to re-lock. Only use this if a gradual change is made to the PLL SS_PLL_CTL_NLOCK DW If set to , set the boot mode to boot from JTAG SS_TEST_MODE_BOOT_JTAG 8 DW If set to , set the PLL to be bypassed SS_TEST_MODE_PLL_BYPASS :6 RO - Reserved : RW Output divider value range from to . OD value. SS_PLL_CTL_POST_DIVISOR : RO - Reserved :8 RW Feedback multiplication ratio, range from (x) to 8 (xFFF). F value. SS_PLL_CTL_FEEDBACK_MUL :6 RO - Reserved : RW Oscilator input divider value range from (x) to 6 (xF). R value. SS_PLL_CTL_INPUT_DIVISOR x6: PLL settings 6 |
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