XM014034B datasheet(3/83 Pages) XMOS

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XU6--QF6A Datasheet

xCORE Multicore Microcontrollers

The xcore.ai series is a comprehensive range of

-bit multicore microcontrollers that

brings the low latency and timing determinism of the xCORE architecture to mainstream

embedded applications. Unlike conventional microcontrollers, xCORE multicore micro-

controllers execute multiple real-time tasks simultaneously and communicate between

tasks using a high speed network. Because xCORE multicore microcontrollers are com-

pletely deterministic when executing from internal memory, you can write software to

implement functions that traditionally require dedicated hardware.

X0Dxx

I/O pins

xTIME

scheduler

Hardware response ports

core

PLL

app

PLL

JTAG

X1Dxx

I/O pins

xTIME

scheduler

Hardware response ports

Internal

SRAM

OTP

ALU (FP + int)

Vector unit

Internal

SRAM

OTP

ALU (FP + int)

Vector unit

xCORE "logical" core

Figure :

XU6--

QF6A block

diagram

Key features of the XU6--QF6A include:

Tiles

: Devices consist of one or more xCORE tiles. Each tile contains between ve and

eight

-bit logical cores with highly integrated I/O and on-chip memory.

Logical cores

Each logical core can execute tasks such as computational code, DSP

code, Floating point operations, Vector operationns, control software (including logic

decisions and executing a state machine) or software that handles I/O. Section 6.

xTIME scheduler

The xTIME scheduler performs functions similar to an RTOS, in hard-

ware. It services and synchronizes events in a core, so there is no requirement for in-

terrupt handler routines. The xTIME scheduler triggers cores on events generated by

hardware resources such as the I/O pins, communication channels and timers. Once

triggered, a core runs independently and concurrently to other cores, until it pauses to

wait for more events. Section 6.

Channels and channel ends

Tasks running on logical cores communicate using chan-

nels formed between two channel ends. Data can be passed synchronously or asyn-

chronously between the channel ends assigned to the communicating tasks. Section

xCONNECT Switch and Links

Between tiles, channel communications are implemented

over a high performance network of xCONNECT Links and routed through a hardware

xCONNECT Switch. Section 6.6

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