Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

XM014034B Datasheet(PDF) 5 Page - Xmos Ltd.

Part # XM014034B
Description  XCore xcore.ai Microcontroller IC 32-Bit 16-Core 2400MIPs 8KB (8K x 8) OTP 60-QFN (7x7)
PDF  83 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  XMOS [Xmos Ltd.]
Direct Link  https://www.xmos.ai/
Logo XMOS - Xmos Ltd.

XM014034B Datasheet(HTML) 5 Page - Xmos Ltd.

  XM014034B Datasheet HTML 1Page - Xmos Ltd. XM014034B Datasheet HTML 2Page - Xmos Ltd. XM014034B Datasheet HTML 3Page - Xmos Ltd. XM014034B Datasheet HTML 4Page - Xmos Ltd. XM014034B Datasheet HTML 5Page - Xmos Ltd. XM014034B Datasheet HTML 6Page - Xmos Ltd. XM014034B Datasheet HTML 7Page - Xmos Ltd. XM014034B Datasheet HTML 8Page - Xmos Ltd. XM014034B Datasheet HTML 9Page - Xmos Ltd. Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 83 page
background image
XU6--QF6A Datasheet
XU6--QF6A Features
Multicore Microcontroller with Advanced Multi-Core RISC Architecture
• 6 real-time logical cores on xCORE tiles
• Cores share up to
MIPS
— Up to
MIPS in dual issue mode
— Up to
MFLOPS
• Each logical core has:
— Guaranteed throughput of between / and /8 of tile MIPS
— 6xbit dedicated registers
•
high-density 6/-bit instructions
— All have single clock-cycle execution (except for divide)
—
x →6-bit MAC instructions for DSP, arithmetic and cryptographic functions
• Vector unit, capable of:
— up to eight word, 6 half-word, or
byte multiply-adds.
— quad complex multiply, or
6 bit-wide multiply-adds.
USB PHY, fully compliant with USB . specication
Application PLL with fractional control
Programmable I/O
•
general-purpose I/O pins, congurable as input or output
— Up to 6 x bit port, x bit port, x 8bit port
— xCONNECT link
• Port sampling rates of up to 6 MHz with respect to an external clock
• 6 channel ends (
per tile) for communication with other cores, on or off-chip
• .8V IO with programmable drive strength
Memory
• MB internal single-cycle SRAM (KB per tile) for code and data storage
• 8KB internal OTP (shared between tiles or split providing KB per tile) for application boot code
Hardware resources
•
clock blocks (6 per tile)
•
timers ( per tile)
• 8 locks ( per tile)
JTAG Module for On-Chip Debug
Security Features
• Programming lock disables debug and prevents read-back of memory contents
• AES bootloader ensures secrecy of IP held on external ash memory
Ambient Temperature Range
• °C to
°C
Speed Grade
•
: 6
MHz; up to
MIPS,
MFLOP/s, 8. GMACC/s
•
: 8
MHz; up to
MIPS, 6
MFLOP/s, . GMACC/s
Power Consumption
•
mA (typical)
6-pin QFN package . mm pitch



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com