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XM014034B Datasheet(PDF) 29 Page - Xmos Ltd.

Part # XM014034B
Description  XCore xcore.ai Microcontroller IC 32-Bit 16-Core 2400MIPs 8KB (8K x 8) OTP 60-QFN (7x7)
PDF  83 Pages
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Manufacturer  XMOS [Xmos Ltd.]
Direct Link  https://www.xmos.ai/
Logo XMOS - Xmos Ltd.

XM014034B Datasheet(HTML) 29 Page - Xmos Ltd.

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XU6--QF6A Datasheet
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General routing and placement guidelines
The following guidelines will help to avoid signal quality and EMI problems on high speed
designs. They relate to a four-layer (Signal, GND, Power, Signal) PCB.
For best results, most of the routing should be done on the top layer (assuming the de-
vices are on the top layer) closest to GND. Reference planes should be below the trans-
mission lines in order to maintain control of the trace impedance.
We recommend that the high-speed clock and high-speed differential pairs are routed
rst before any other routing. When routing high speed signals, the following guidelines
should be followed:
High speed differential pairs should be routed together.
High-speed signal pair traces should be trace-length matched.
Ensure that high speed signals (clocks, differential pairs) are routed as far away from
off-board connectors as possible.
High-speed clock and periodic signal traces that run parallel should be at least a dis-
tance S3 away from D+/D- (see Figure 8 and Figure
).
Low-speed and non-periodic signal traces that run parallel should be at least S2 away
from D+/D- (see Figure 8 and Figure
).
Route high speed signals on the top of the PCB wherever possible.
Route high speed traces over continuous power planes, with no breaks. If a trade-off
must be made, changing signal layers is preferable to crossing plane splits.
Follow the 20 × h rule; keep traces 20 × h (the height above the power plane) away
from the edge of the power plane.
Use a minimum of vias in high speed traces.
Avoid corners in the trace. Where necessary, rather than turning through a
degree
angle, use two
degree turns or an arc.
DO NOT route differential pair traces near clock sources, clocked circuits or magnetic
devices.
Avoid stubs on high speed signals.
.
Land patterns and solder stencils
The package is a 6 pin Quad Flat No lead Package (QFN) on a .mm pitch with four
VDD paddles and an exposed ground paddle.
The land patterns and solder stencils will depend on the PCB manufacturing process. We
recommend you design them with using the IPC specications “Generic Requirements
for Surface Mount Design and Land Pattern Standards”
IPC-B. This standard aims
8



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