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STC12LE5616AD Datasheet(PDF) 196 Page - STCmicro Technology Co,.Ltd |
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STC12LE5616AD Datasheet(HTML) 196 Page - STCmicro Technology Co,.Ltd |
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196 / 377 page ![]() 1. Serial Port 1 (UART1) Control Register: SCON and PCON Serial port 1 of STC12C5620AD series has two control registers: Serial port control register (SCON) and PCON which used to select Baud-Rate SCON: Serial port Control Register (Bit-Addressable) SFR name Address bit B7 B6 B5 B4 B3 B2 B1 B0 SCON 98H name SM0/FE SM1 SM2 REN TB8 RB8 TI RI FE: Framing Error bit. The SMOD0 bit must be set to enable access to the FE bit 0: The FE bit is not cleared by valid frames but should be cleared by software. 1: This bit set by the receiver when an invalid stop bit id detected. SM0,SM1 : Serial Port Mode Bit 0/1. SM0 SM1 Description Baud rate 0 0 8-bit shift register SYSclk/12 0 1 8-bit UART variable 1 0 9-bit UART SYSclk/64 or SYSclk/32(SMOD=1) 1 1 9-bit UART variable SM2 : Enable the automatic address recognition feature in mode 2 and 3. If SM2=1, RI will not be set unless the received 9th data bit is 1, indicating an address, and the received byte is a Given or Broadcast address. In mode1, if SM2=1 then RI will not be set unless a valid stop Bit was received, and the received byte is a Given or Broadcast address. In mode 0, SM2 should be 0. REN : When set enables serial reception. TB8 : The 9th data bit which will be transmitted in mode 2 and 3. RB8 : In mode 2 and 3, the received 9th data bit will go into this bit. TI : Transmit interrupt flag. Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the UART0 in- terrupt is enabled, setting this bit causes the CPU to vector to the UART0 interrupt service routine. This bit must be cleared manually by software. RI : Receive interrupt flag. Set to ‘1’ by hardware when a byte of data has been received by UART0 (set at the STOP bit sam-pling time). When the UART0 interrupt is enabled, setting this bit to ‘1’ causes the CPU to vector to the UART0 interrupt service routine. This bit must be cleared manually by software. SMOD/PCON.7 in PCON register can be used to set whether the baud rates of mode 1, mode2 and mode 3 are doubled or not. PCON: Power Control register (Non bit-addressable) SFR name Address bit B7 B6 B5 B4 B3 B2 B1 B0 PCON 87H name SMOD SMOD0 LVDF POF GF1 GF0 PD IDL SMOD: double Baud rate control bit. 0 : Disable double Baud rate of the UART. 1 : Enable double Baud rate of the UART in mode 1,2,or 3. SMOD0: Frame Error select. 0 : SCON.7 is SM0 function. 1 : SCON.7 is FE function. Note that FE will be set after a frame error regardless of the state of SMOD0. 196 |
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