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PI7C8150AND Datasheet(PDF) 103 Page - Pericom Semiconductor Corporation |
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PI7C8150AND Datasheet(HTML) 103 Page - Pericom Semiconductor Corporation |
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103 / 111 page  PI7C8150A 2-PORT PCI-TO-PCI BRIDGE Page 103 of 111 APRIL 2006 – Revision 1.1 TCK. The value of the test mode state (TMS) input signal at a rising edge of TCK controls the sequence of state changes. The TAP controller is initialized after power-up by applying a low to the TRST_L pin. In addition, the TAP controller can be initialized by applying a high signal level on the TMS input for a minimum of five TCK periods. For greater detail on the behavior of the TAP controller, test logic in each controller state and the state machine and public instructions, refer to the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture document (available from the IEEE). Table 16-2. JTAG Boundary Register Order Boundary-Scan Register Number Pin Name Pin Number Type 0 S_AD[0] 137 BIDIR 1 S_AD[1] 138 BIDIR 2 S_AD[2] 140 BIDIR 3 S_AD[3] 141 BIDIR 4 S_AD[4] 143 BIDIR 5 S_AD[5] 144 BIDIR 6 S_AD[6] 146 BIDIR 7 S_AD[7] 147 BIDIR 8 S_CBE[0] 149 BIDIR 9 S_AD[8] 150 BIDIR 10 S_AD[9] 152 BIDIR 11 S_M66EN 153 OUTPUT 12 S_AD[10] 154 BIDIR 13 S_AD[11] 159 BIDIR 14 S_AD[12] 161 BIDIR 15 S_AD[13] 162 BIDIR 16 S_AD[14] 164 BIDIR 17 S_AD[15] 165 BIDIR 18 CONTROL 19 S_CBE[1] 167 BIDIR 20 S_PAR 168 BIDIR 21 S_SERR_L 169 INPUT 22 S_PERR_L 171 BIDIR 23 S_LOCK_L 172 BIDIR 24 S_STOP_L 173 BIDIR 25 CONTROL 26 S_DEVSEL_L 175 BIDIR 27 S_TRDY_L 176 BIDIR 28 S_IRDY_L 177 BIDIR 29 S_FRAME_L 179 BIDIR 30 S_CBE[2] 180 BIDIR 31 S_AD[16] 182 BIDIR 32 S_AD[17] 183 BIDIR 33 S_AD[18] 185 BIDIR 34 S_AD[19] 186 BIDIR 35 S_AD[20] 188 BIDIR 36 S_AD[21] 189 BIDIR 37 S_AD[22] 191 BIDIR 38 S_AD[23] 192 BIDIR 39 S_CBE[3] 194 BIDIR 40 S_AD[24] 195 BIDIR 41 S_AD[25] 197 BIDIR 42 S_AD[26] 198 BIDIR 43 S_AD[27] 200 BIDIR 44 S_AD[28] 201 BIDIR 45 S_AD[29] 203 BIDIR 46 S_AD[30] 204 BIDIR 47 CONTROL 06-0057 |
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