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TUSB7340 Datasheet(PDF) 45 Page - Texas Instruments |
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TUSB7340 Datasheet(HTML) 45 Page - Texas Instruments |
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45 / 122 page ![]() 8.1.18 Interrupt Line Register This read/write register is programmed by the system and indicates to the software which interrupt line the TUSB73X0 has been assigned. The default value of this register is FFh, indicating that an interrupt line has not yet been assigned to the function PCI register offset: 3Ch Register type: Read-only Default value: FFh Table 8-25. PCI Register 3Ch Bit No. 7 6 5 4 3 2 1 0 Reset State 1 1 1 1 1 1 1 1 8.1.19 Interrupt Pin Register The Interrupt Pin register is read-only 01h indicating that the TUSB73X0 uses INTA. PCI register offset: 3Dh Register type: Read-only Default value: 01h Table 8-26. PCI Register 3Dh Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 1 8.1.20 Min Grant Register This read-only register has no meaningful context for a PCI Express device and returns zeros when read. PCI register offset: 3Eh Register type: Read-only Default value: 00h Table 8-27. PCI Register 3Eh Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 8.1.21 Max Latency Register This read-only register has no meaningful context for a PCI Express device and returns zeros when read. PCI register offset: 3Fh Register type: Read-only Default value: 00h Table 8-28. PCI Register 3Fh Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 www.ti.com TUSB7320, TUSB7340 SLLSE76Q – MARCH 2011 – REVISED MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: TUSB7320 TUSB7340 |
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