TUSB7340 datasheet(79/122 Pages) TI2

79 / 122 page

Table 8-115. Bit Descriptions – Uncorrectable Error Severity Register (continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

CPL_TIMEOUT_SEVR(1)

Completion Timeout Severity.

0 – Error Condition is signaled using ERR_NONFATAL

1 – Error Condition is signaled using ERR_FATAL

FC_ERROR_SEVR(1)

Flow Control Error Severity. 0 – Error Condition is signaled using

ERR_NONFATAL1 – Error Condition is signaled using ERR_FATAL

PSN_TLP_SEVR(1)

Poisoned TLP Severity.

0 – Error Condition is signaled using ERR_NONFATAL

1 – Error Condition is signaled using ERR_FATAL

11:6

RSVD

Reserved. Returns zeros when read.

RSVD

Reserved. Returns 1 when read.

DLL_ERROR_SEVR(1)

Data Link Protocol Error Severity.

0 – Error Condition is signaled using ERR_NONFATAL

1 – Error Condition is signaled using ERR_FATAL

3:0

RSVD

Reserved. Returns zeros when read.

(1)

This bit is reset by a PCI Express reset (PERST), a GRST, or the internally generated power-on-reset.

8.2.7 Correctable Error Severity Register

The Correctable Error Status Register reports the status of individual errors as they occur. Software may clear

these bits only by writing a 1 to the desired location.

PCI Express Extended Register Offset: 110h

Default value: 0000 0000h

Table 8-116. PCI Express Extended Register 110h

Bit

No.

Reset

State

Bit

No.

Reset

State

Table 8-117. Bit Descriptions – Correctable Error Severity Register

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:14

RSVD

Reserved. Returns zeros when read.

ANFES(1)

rcu

Advisory Non-Fatal Error Status. This bit is asserted when an Advisory

Non-Fatal Error has been reported.

REPLAY_TMOUT(1)

rcu

Replay Timer Timeout. This bit is asserted when the replay timer expires

for a pending request or completion that has not been acknowledged.

11:9

RSVD

Reserved. Returns zeros when read.

REPLAY_ROLL(1)

rcu

REPLAY_NUM Rollover. This bit is asserted when the replay counter

rolls over when a pending request or completion has not been

acknowledged.

BAD_DLLP(1)

rcu

Bad DLLP Error. This bit is asserted when an 8b/10b error was detected

by the PHY during the reception of a DLLP.

BAD_TLP(1)

rcu

Bad TLP Error. This bit is asserted when an 8b/10b error was detected

by the PHY during the reception of a TLP.

5:1

RSVD

Reserved. Returns zeros when read.

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TUSB7320, TUSB7340

SLLSE76Q – MARCH 2011 – REVISED MARCH 2024

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