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TUSB7340 Datasheet(PDF) 88 Page - Texas Instruments |
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TUSB7340 Datasheet(HTML) 88 Page - Texas Instruments |
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88 / 122 page  Table 8-136. HC Structural Parameters 3 Description BIT FIELD NAME ACCESS DESCRIPTION 31:16 U2_EXIT_LAT r U2 Device Exit Latency. This field is 07FFh to indicate that the worst case latency for the TUSB73X0 to transition from U2 to U0 is 2047 µs. 15:8 RSVD r Reserved. Returns zeros when read. 7:0 U1_EXIT_LAT r U1 Device Exit Latency. This field is 0Ah to indicate that the worst case latency for the TUSB73X0 to transition a root hub Port Link State from U1 to U0 is 10 µs. 8.3.2.6 Host Controller Capability Parameters This read only register defines capability parameters supported by the TUSB73X0. BAR0 register offset: 10h Register type: Read-Only Default value: 0270 102Xh Table 8-137. HC Capability Register 10h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 1 1 1 1 0 0 0 0 0 1 1 0 x 1 0 1 Table 8-138. HC Capability Parameters Description BIT FIELD NAME ACCESS DESCRIPTION 31:16 XECP r xHCI Extended Capabilities Pointer. This field is 0270h to indicate that the beginning of the first xHCI Extended Capability is at an offset of 09C0h from the address programmed into the Base Address Register 0. 15:12 MAX_PSA_SIZE r Maximum Primary Stream Array Size. This field is 1111 to indicate that the TUSB73X0 supports a Primary Stream Array size of 64K. 11:10 RSVD r Reserved. Returns zeros when read. 9 SBD r Secondary Bandwidth Domain Reporting. This bit is 0 to indicate that the TUSB73X0 does not support Secondary Bandwidth Domain reporting. 8 FSE r Force Stopped Event. This bit is 0 to indicate that the TUSB73X0 does not support Force Stopped Events. 7 NSS r No Secondary SID Support. This bit is 0 to indicate that the TUSB73X0 supports Secondary Stream ID decoding. 6 LTC r Latency Tolerance Messaging Capability. This bit is 1 to indicate that the TUSB73X0 supports Latency Tolerance Messaging. 5 LHRC r Light HC Reset Capability. This bit is 1 to indicate that the TUSB73X0 supports Light Host Controller Resets. 4 PIND r Port Indicators. This bit is 0 to indicate that the TUSB73X0 does not support port indicators. 3 PPC r Port Power Control. This value of this bit is determined by the PPC_NOT_PRESENT bit in the USB Control Register. 2 CSZ r Context Size. This bit is 1 to indicate that the TUSB73X0 uses 64 byte Context data structures. 1 BNC r Bandwidth Negotiation Capability. This bit is 0 to indicate that the TUSB73X0 does not implement Bandwidth Negotiation. TUSB7320, TUSB7340 SLLSE76Q – MARCH 2011 – REVISED MARCH 2024 www.ti.com 88 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TUSB7320 TUSB7340 |
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