TUSB7340 datasheet(63/122 Pages) TI2

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8.1.53 GPIO Control Register

This register is used to control the direction of the eight GPIO pins. This register is reset by a PCI Express reset

(PERST#), a GRST#, or the internally-generated power-on-reset.

PCI register offset: B4h

Default value: 0000h

Table 8-79. PCI Register B4h

Bit

No.

Reset

State

Table 8-80. GPIO Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:4

RSVD

Reserved. Returns zero when read.

GPIO3_DIR(1)

GPIO 3 Data Direction. This bit selects whether GPIO3 is in input or

output mode.

0 – Input

1 – Output

GPIO2_DIR(1)

GPIO 2 Data Direction. This bit selects whether GPIO2 is in input or

output mode.

0 – Input

1 – Output

GPIO1_DIR(1)

GPIO 1 Data Direction. This bit selects whether GPIO1 is in input or

output mode.

0 – Input

1 – Output

GPIO0_DIR(1)

GPIO 0 Data Direction. This bit selects whether GPIO0 is in input or

output mode.

0 – Input

1 – Output

(1)

This bit is reset by a PCI Express reset (PERST), a GRST, or the internally generated power-on-reset.

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TUSB7320, TUSB7340

SLLSE76Q – MARCH 2011 – REVISED MARCH 2024

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