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TUSB7340 Datasheet(PDF) 77 Page - Texas Instruments |
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TUSB7340 Datasheet(HTML) 77 Page - Texas Instruments |
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77 / 122 page  Table 8-111. Custom PHY Transmit/Receive Control Register Description (continued) BIT FIELD NAME ACCESS DESCRIPTION 11:5 RSVD r Reserved. Returns zeros when read. 4 DLL_ERROR(1) rcu Data Link Protocol Error. This bit is asserted if a data link layer protocol error is detected. 3:0 RSVD r Reserved. Returns zeros when read. (1) This bit is reset by a PCI Express reset (PERST), a GRST, or the internally generated power-on-reset. 8.2.5 Uncorrectable Error Mask Register The Uncorrectable Error Mask Register controls the reporting of individual errors as they occur. When a bit is set to one, the corresponding error condition will not be logged, and does not update any of the status bits within the Extended Error Reporting Capability block. PCI Express Extended Register Offset: 108h Register type: Read-Only, Read/Write Default value: 0000 0000h Table 8-112. PCI Express Extended Register 108h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 8-113. Bit Descriptions – Uncorrectable Error Mask Register BIT FIELD NAME ACCESS DESCRIPTION 31:21 RSVD r Reserved. Returns zeros when read. 20 UR_ERROR_MASK(1) rw Unsupported Request Error Mask. 0 – Error Condition is Unmasked 1 – Error Condition is Masked 19 ECRC_ERROR_MASK(1) rw Extended CRC Error Mask. 0 – Error Condition is Unmasked 1 – Error Condition is Masked 18 MAL_TLP_MASK(1) rw Malformed TLP Mask. 0 – Error Condition is Unmasked 1 – Error Condition is Masked 17 RX_OVERFLOW_MASK(1) rw Receiver Overflow Mask. 0 – Error Condition is Unmasked 1 – Error Condition is Masked 16 UNXP_CPL_MASK(1) rw Unexpected Completion Mask. 0 – Error Condition is Unmasked 1 – Error Condition is Masked 15 CPL_ABORT_MASK(1) rw Completer Abort Mask. 0 – Error Condition is Unmasked 1 – Error Condition is Masked 14 CPL_TIMEOUT_MASK(1) rw Completion Timeout Mask. 0 – Error Condition is Unmasked 1 – Error Condition is Masked 13 FC_ERROR_MASK(1) rw Flow Control Error Mask. 0 – Error Condition is Unmasked 1 – Error Condition is Masked www.ti.com TUSB7320, TUSB7340 SLLSE76Q – MARCH 2011 – REVISED MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 77 Product Folder Links: TUSB7320 TUSB7340 |
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