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TUSB7340 Datasheet(PDF) 5 Page - Texas Instruments |
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TUSB7340 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 122 page  Table 4-1. Clock and Reset Signals PIN TYPE DESCRIPTION NAME TUSB7320 TUSB7340 CLOCK AND RESET SIGNALS GRST# A15 A15 I PU Global power reset. This reset brings all of the TUSB73x0 internal registers to their default states. When GRST# is asserted, the device is completely nonfunctional. GRST# should be asserted until all power rails are valid at the device. If a 24 MHz or 48 MHz reference clock is used instead of a crystal, GRST# must remain asserted until the 24 MHz or 48 MHz clock is stable. XI A23 A23 I Crystal input. This terminal is the crystal input for the internal oscillator. The input may alternately be driven by the output of an external oscillator. When using a crystal a 2-MΩ feedback resistor is required between XI and XO. XO A22 A22 O Crystal output. This terminal is crystal output for the internal oscillator. If XI is driven by an external oscillator this pin may be left unconnected. When using a crystal a 2-MΩ feedback resistor is required between XI and XO. FREQSEL B14 B14 I Frequency select. This terminal indicates the oscillator input frequency and is used to configure the correct PLL multiplier. This pin should be set low for normal operation. PCIE_REFCLKP A45 A45 I PCI Express Reference Clock. PCIE_REFCLKP and PCIE_REFCLKN comprise the differential input pair for the 100-MHz system reference clock. PCIE_REFCLKN B41 B41 I PERST# A40 A40 I PCI Express Reset Input. The PERST# signal is used to signal when the system power is stable. The PERST# signal is also used to generate an internal power on reset PCI EXPRESS SIGNALS PCIE_TXP B38 B38 O PCI Express transmitter differential pair (positive). PCIE_TXN A41 A41 O PCI Express transmitter differential pair (negative). PCIE_RXP B39 B39 I PCI Express receiver differential pair (positive). PCIE_RXN A42 A42 I PCI Express receiver differential pair (negative). WAKE# B35 B35 O Wake. Wake is an active low signal that is driven low to reactivate the PCI Express link hierarchy’s main power rails and reference clocks. Note: WAKE# is not a failsafe I/O and should not be connected to a 3.3-V auxiliary supply while VDD33 is not present. CLKREQ# B36 B36 O PCI Express REFCLK Request signal. Note: CLKREQ# is not a failsafe I/O and should not be connected to a 3.3-V auxiliary supply while VDD33 is not present. USB DOWNSTREAM SIGNALS USB_SSTXP_DN1 A17 A17 O USB SuperSpeed transmitter differential pair (positive). Note: When routing, it is permissible to swap the positive and negative signals in Port 1 SSTX differential pair. USB_SSTXN_DN1 B15 B15 O USB SuperSpeed transmitter differential pair (negative). Note: When routing, it is permissible to swap the positive and negative signals in Port 1 SSTX differential pair. USB_SSRXP_DN1 A18 A18 I USB SuperSpeed receiver differential pair (positive). Note: When routing, it is permissible to swap the positive and negative signals in Port 1 SSRX differential pair. USB_SSRXN_DN1 B16 B16 I USB SuperSpeed receiver differential pair (negative). Note: When routing, it is permissible to swap the positive and negative signals in Port 1 SSRX differential pair. USB_DP_DN1 A20 A20 I/O USB High-speed differential transceiver (positive). USB_DM_DN1 B18 B18 I/O USB High-speed differential transceiver (negative). PWRON1# B33 B33 O PD USB DS Port 1 Power On Control for Downstream Power. The terminal is used to control the downstream power switch. If the PWRON_POLARITY bit is set to 1, this pin is active high and the internal pull-down is disabled. This pin may be at low impedance when power rails are removed. OVERCUR1# A36 A36 I PU USB DS Port 1 Overcurrent Detection. 0: overcurrent detected; 1: overcurrent not detected www.ti.com TUSB7320, TUSB7340 SLLSE76Q – MARCH 2011 – REVISED MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TUSB7320 TUSB7340 |
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