TUSB7340 datasheet(81/122 Pages) TI2

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8.2.8 Correctable Error Mask Register

The Correctable Error Status Register reports the status of individual errors as they occur. Software may clear

these bits only by writing a 1 to the desired location.

PCI Express Extended Register Offset: 114h

Default value: 0000 2000h

Table 8-118. PCI Express Extended Register 114h

Bit

No.

Reset

State

Bit

No.

Reset

State

Table 8-119. Bit Descriptions – Correctable Error Mask Register

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:14

RSVD

Reserved. Returns zeros when read.

ANFEM(1)

Advisory Non-Fatal Error Mask.

0 – Error Condition is Unmasked

1 – Error Condition is Masked

REPLAY_TMOUT_MASK(1)

Replay Timer Timeout Mask.

0 – Error Condition is Unmasked

1 – Error Condition is Masked

11:9

RSVD

Reserved. Returns zeros when read.

REPLAY_ROLL_MASK(1)

REPLAY_NUM Rollover Mask.

0 – Error Condition is Unmasked

1 – Error Condition is Masked

BAD_DLLP_MASK(1)

Bad DLLP Error Mask.

0 – Error Condition is Unmasked

1 – Error Condition is Masked

BAD_TLP_MASK(1)

Bad TLP Error Mask.

0 – Error Condition is Unmasked

1 – Error Condition is Masked

5:1

RSVD

Reserved. Returns zeros when read.

RX_ERROR_MASK(1)

Receiver Error Mask.

0 – Error Condition is Unmasked

1 – Error Condition is Masked

(1)

This bit is reset by a PCI Express reset (PERST), a GRST, or the internally generated power-on-reset.

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TUSB7320, TUSB7340

SLLSE76Q – MARCH 2011 – REVISED MARCH 2024

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