TDA9983BHWSLASH8SLASHC1 datasheet(63/119 Pages) NXP

63 / 119 page

TDA9983B_1

Product data sheet

Rev. 01 — 20 May 2008

63 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

9.5.2 Current page address register

9.6 Information frames and packets page register deﬁnitions

The current page address for the Information frames and packets page is 10h.

The conﬁguration of the registers for this page is given in Table 83.

Table 81.

SEL_CLK register (address 11h) bit description

Legend: * = default value

Bit

Symbol

Access

Value

Description

7 to 4

R/W

0000*

undeﬁned

ENA_SC_CLK

R/W

enable scaler clocks

disable scaler clocks (sc_clk_m, clk1_m)

enable scaler clocks (sc_clk_m, clk1_m)

2 to 1

SEL_VRF_CLK[1:0]

R/W

select video reformatter clock

00*

vrf_clk_m = not tmdsclkpo;

sc_clk_m = tmdsclkpo

vrf_clk_m = scaclko_pllscgon;

sc_clk_m = not scaclko_pllscgon

vrf_clk_m = scaclko_tmdsclkn;

sc_clk_m = not scaclko_tmdsclkn

vrf_clk_m = scaclko_tmdsclkn;

sc_clk_m = not scaclko_tmdsclkn

SEL_CLK1

R/W

select clock 1

clk1_m = not (plldeo)

clk1_m = plldeo_div2

Table 82.

CURPAGE_ADR register (address FFh) bit description

Legend: * = default value

Bit

Symbol

Access

Value

Description

7 to 0

CURPAGE_ADR[7:0]

00h*

current page address: selects the current

memory page

TDA9983BHW/8/C1 Datasheet(PDF) 63 Page - NXP Semiconductors

TDA9983BHW/8/C1 Datasheet(HTML) 63 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL