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TDA9983BHW/8/C1 Datasheet(PDF) 91 Page - NXP Semiconductors

Part # TDA9983BHW/8/C1
Description  HDMI transmitter up to 150 MHz pixel rate with 3 쨈 8-bit video inputs and 4 쨈 I2S-bus with S/PDIF
PDF  119 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

TDA9983BHW/8/C1 Datasheet(HTML) 91 Page - NXP Semiconductors

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TDA9983B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 20 May 2008
91 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
9.7.2 ISRC packets registers
Below is an example of use. Please refer to
HDMI 1.2a specification for the correct
definition of data bytes.
See
HDMI 1.2a specification, section 8.8 for rules regarding the use of the ISRC packets.
Table 101. CH_STAT_B_x channel status bytes 0, 1, 3 and 4 registers (address 14h to 17h) bit description
Legend: * = default value
Address
Register
Bit
Symbol
Access
Value
Description
channel status byte x:
x = 0 to 4
14h
CH_STAT_B_0
7 to 0
CH_STAT_BYTE_0[7:0]
R/W
00h*
byte 0
15h
CH_STAT_B_1
7 to 0
CH_STAT_BYTE_1[7:0]
R/W
00h*
byte 1
16h
CH_STAT_B_3
7 to 0
CH_STAT_BYTE_3[7:0]
R/W
00h*
byte 3
17h
CH_STAT_B_4
7 to 0
CH_STAT_BYTE_4[7:0]
R/W
00h*
byte 4
Table 102. CH_STAT_B_2_APx_n channel status byte 2 registers (address 18h to 1Fh) bit description
Legend: * = default value
Address
Register
Bit
Symbol
Access
Value
Description
channel status byte 2
of audio port x:
x = 0 to 3
18h
CH_STAT_B_2_AP0_L
7 to 0
CH_STAT_BYTE_2_AP0_L[7:0]
R/W
00h*
audio port 0 left
19h
CH_STAT_B_2_AP0_R
7 to 0
CH_STAT_BYTE_2_AP0_R[7:0]
R/W
00h*
audio port 0 right
1Ah
CH_STAT_B_2_AP1_L
7 to 0
CH_STAT_BYTE_2_AP1_L[7:0]
R/W
00h*
audio port 1 left
1Bh
CH_STAT_B_2_AP1_R
7 to 0
CH_STAT_BYTE_2_AP1_R[7:0]
R/W
00h*
audio port 1 right
1Ch
CH_STAT_B_2_AP2_L
7 to 0
CH_STAT_BYTE_2_AP2_L[7:0]
R/W
00h*
audio port 2 left
1Dh
CH_STAT_B_2_AP2_R
7 to 0
CH_STAT_BYTE_2_AP2_R[7:0]
R/W
00h*
audio port 2 right
1Eh
CH_STAT_B_2_AP3_L
7 to 0
CH_STAT_BYTE_2_AP3_L[7:0]
R/W
00h*
audio port 3 left
1Fh
CH_STAT_B_2_AP3_R
7 to 0
CH_STAT_BYTE_2_AP3_R[7:0]
R/W
00h*
audio port 3 right
Table 103. ISRC1 packet registers (address 20h to 3Eh) bit description
Legend: * = default value
Address Register
Bit
Symbol
Access Value Description
20h
ISRC1_PACKET_
TYPE
7 to 0 ISRC1_PACKET_TYPE[7:0]
R/W
05h*
ISRC1 packet type: packet type
of the ISRC1 packet
21h
ISRC1_CTRL
7
ISRC_CONT
R/W
0*
ISRC continued: ISRC continued
in next packet
6
ISRC_VALID
R/W
0*
ISRC valid: ISRC status and data
are valid
5 to 3 ISRC1_RSVD[5:3]
R/W
000*
ISRC1 reserved: reserved (shall
be zero)
2 to 0 ISRC_STATUS[2:0]
R/W
000*
ISRC status
001
starting position
010
intermediate position
100
ending position



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