TDA9983BHWSLASH8SLASHC1 datasheet(89/119 Pages) NXP

89 / 119 page

TDA9983B_1

Product data sheet

Rev. 01 — 20 May 2008

89 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

3 to 2

CTL_CODE[1:0]

R/W

control code: force CTL[1:0]

CTL[1:0] = 00 (DVI mode)

01*

CTL[1:0] = 01 (advised to use in case of

HDMI mode)

CTL[1:0] = 10 (only for debugging purposes)

CTL[1:0] = 11 (only for debugging purposes)

1 to 0

DC_CTL[1:0]

R/W

disparity counter control

00*

video guard band initializes disparity_cnt

video_data_enable enables disparity_cnt

free-running disparity_cnt

undeﬁned

Table 99.

DIP_FLAGS register (address 0Eh) bit description

Legend: * = default value

Bit

Symbol

Access

Value

Description

FORCE_NULL

R/W

force null

no speciﬁc action

insert null-packets continuously

NULL

R/W

null

no speciﬁc action

insert one null-packet (this bit is reset by

internal control)

R/W

-: data packet header/contents as speciﬁed by

registers 80h to 9Eh

no speciﬁc action

insert InfoFrame in ﬁrst free slot after the

keepout window

ACP

R/W

audio content protection: data packet

header/contents as speciﬁed by registers 60h

to 7Eh (see Table 105)

no speciﬁc action

insert ’acp’ in ﬁrst free slot after the keepout

window

ISRC2

R/W

international standard recording code 2:

data packet header/contents as speciﬁed by

registers 40h to 5Eh (see Table 104)

no speciﬁc action

insert ’isrc2’ in ﬁrst free slot after the keepout

window

Table 98.

ENC_CNTRL register (address 0Dh) bit description …continued

Legend: * = default value

Bit

Symbol

Access

Value

Description

TDA9983BHW/8/C1 Datasheet(PDF) 89 Page - NXP Semiconductors

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