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C5NPD0-DS Datasheet(PDF) 27 Page - Freescale Semiconductor, Inc |
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C5NPD0-DS Datasheet(HTML) 27 Page - Freescale Semiconductor, Inc |
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27 / 100 page ![]() V 04 C5NPD0-DS/D Rev 04 Chapter 2 SIGNAL DESCRIPTIONS Signal Summary There are ten functional groupings of signals in the C-5 network processor: • Clock — 11 pins • Channel Processors (CP0 - CP15) — 16x7 = 112 pins • Executive Processor (XP) — 57 pins – PCI Interface — 50 pins – PROM Interface — 4 pins – Serial Bus Interface — 2 pins – General System Interface — 1 pin • Fabric Processor (FP) — 80 pins • Buffer Management Unit (BMU) — 161 pins • Table Lookup Unit (TLU) — 100 pins • Queue Management Unit (QMU) — 55 pins • Power — 233 pins • Test — 18 pins • No connection (NC) — 11 pins Two of the sections (CPs and FP) are configurable, depending on the type of device being implemented. Pinout Diagram The C-5 NP contains 838 pins as shown in Figure 2. These pin numbers are referenced throughout the remaining chapter. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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