C5NPD0-DS datasheet(65/100 Pages) FREESCALE

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JTAG Support

V 04

Figure 8 Cell Design That Can Be Used for Both Input and Output Pins

IDcode Register

The C-5 NP implements a standard 32bit JTAG identification register. Table 32 lists the

value of the code for full identification and its sub-components.

The concatenated 32bit value is hexidecimal 0000232d.

JTAG Instruction Register

The C-5 NP contains a 4bit instruction register. Table 33 lists the instructions that are

supported.

From

System

To next cell

System

Logic

Shift DR

From last cell

Clock

Update DR

Node

Table 32 JTAG Identification Code and Its Sub-components

FIELD NAME

WIDTH

BIT POSITIONS

BINARY VALUE

Version

31-28

0000

Part Number

27-12

0000_0000_0000_0010

Manufacturer Identity

11-1

001_1001_0110

LSB

Table 33 Instruction Register Instructions

INSTRUCTION MNEMONIC

SELECTED REGISTER

INSTRUCTION OPCODE

Extest

Boundary Scan

0000

Idcode

Identification Register

0001

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