C5NPD0-DS datasheet(86/100 Pages) FREESCALE

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CHAPTER 3: ELECTRICAL SPECIFICATIONS

C5NP

BMU Timing

Specifications

The BMU timing specifications are shown in Figure 23 and described in Table 51.

The BMU synchronous DRAM interface is PC100-compliant and designed to work with

industry standard SDRAM components with 12 or fewer address lines. The information

below is intended to provide the output, setup, and hold data required to design this

interface without duplicating the transaction waveform diagrams in SDRAM data sheets.

Tfrco

FRXCTL Output

1.0

3.4

Tfrcz

FRXCTL Clk to Tri*

1.8

5.5

Tfrcv

FRXCTL Clk to Driven*

1.3

5.5

Tfrds

FIN Setup

4.0

1.5

Utopia2 Mode

All other modes

Tfrdh

FIN Hold

0.5

Tftc

FTX Cycle Time

9.0

Tftcs

FTXCTL Setup

4.0

1.5

Utopia2 Mode

All other modes

Tftch

FTXCTL Hold

0.5

Tftco

FTXCTL Output

1.0

3.6

Tftcz

FTXCTL Clk to Tri*

1.7

5.5

Tftcv

FTXCTL Tri to Driven*

1.3

5.5

Tftdo

FOUT Output

1.0

3.6

* Not fully tested, values based on design/characterization.

Table 50 Fabric Processor Timing Description (continued)

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

COMMENT

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