C5NPD0-DS datasheet(33/100 Pages) FREESCALE

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Pin Descriptions Grouped by Function

V 04

Gigabit Ethernet (GMII) Configuration

Gigabit Ethernet Media Independent Interface (GMII) is configured in one of two ways:

1 Use one CP cluster when density is more important than wire-speed performance

because you can then implement up to four Gigabit Ethernet ports per C-5 NP.

2 Use two CP clusters for wire-speed performance and additional processing power. You

can implement up to two Gigabit Ethernet ports per C-5 NP.

Table 9 lists the possible CP cluster combinations you can use and Figure 3 shows receive

and transmit pin configurations by cluster. Table 10 lists the signals and pinouts for

Gigabit Ethernet (GMII).

Table 8 10/100 Ethernet Signals

SIGNAL NAME*

PIN #

TOTAL

TYPE

I/O

LABEL

SIGNAL DESCRIPTION

CPn_0

Table 6

LVTTL

REF_CLK

Transmit and Receive Clock (50MHz)

CPn_1

Table 6

LVTTL

CRS_DV

Carrier Sense (CRS)/ Receive Data Valid (RX_DV). CRS indicates that

traffic is on the link, and is asserted if the signal is a 1 or an

alternating 1010... RX_DV indicates that a receive frame is in

progress and the data present on the RXD pins is valid. It is

asserted if this signal is a 1 for more than one cycle.

CPn_2

Table 6

LVTTL

TXD(0)

Transmit Data 0 (first on wire)

CPn_3

Table 6

LVTTL

TXD(1)

Transmit Data 1 (second on wire)

CPn_4

Table 6

LVTTL

RXD(0)

Receive Data 0 (first on wire)

CPn_5

Table 6

LVTTL

RXD(1)

Receive Data 1 (second on wire)

CPn_6

Table 6

LVTTL

TX_EN

Transmit Enable. When asserted, the data on TXD is encoded and

transmitted on the twisted pair cable.

TOTAL PINS

* n can be from 0 to 15. See Table 6.

Table 9 Transmit and Receive Pin Combinations for Gigabit Ethernet and Fibre Channel

CLUSTER

SINGLE CLUSTER MODE (TBI OR GMII)

TWO CLUSTER MODE (GMII)*

* The Two Cluster Mode column lists typical configurations. Any cluster can be set up to either receive

or transmit. So you could configure a dual cluster mode where cluster 0 receives and cluster 3

transmits.

Port 1 Tx and Rx

Port 1 Tx

Port 2 Tx and Rx

Port 1 Rx

Port 3 Tx and Rx

Port 2 Tx

Port 4 Tx and Rx

Port 2 Rx

Freescale Semiconductor, Inc.

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