C5NPD0-DS datasheet(35/100 Pages) FREESCALE

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Pin Descriptions Grouped by Function

V 04

Gigabit Ethernet and Fibre Channel TBI Configuration

1000BASE-T Gigabit Ethernet and Fibre Channel TBI is implemented in much the same

way as Gigabit Ethernet (GMII). Table 9 shows the possible CP pin combinations you can

CPn+1_4

Table 6 1

LVTTL

TXD(6)

Transmit Data

CPn+1_5

Table 6 1

LVTTL

TXD(7)

Transmit Data (byte-wide receive data, most significant bit)

CPn+1_6

Table 6 1

LVTTL

TX_ER

Transmit Error. Asserting TX_ER when TX_EN is a 1 causes

transmission of the designated “bad code” in lieu of the normal

encoded data on the twisted pair data.

CPn+2_0

Table 6 1

CPn+2_1

Table 6 1

LVTTL

RCLK

Receive Clock (125MHz)

CPn+2_2

Table 6 1

LVTTL

RXD(0)

Receive Data (byte-wide receive data, least significant bit)

CPn+2_3

Table 6 1

LVTTL

RXD(1)

Receive Data

CPn+2_4

Table 6 1

LVTTL

RXD(2)

Receive Data

CPn+2_5

Table 6 1

LVTTL

RXD(3)

Receive Data

CPn+2_6

Table 6 1

LVTTL

RX_DV

Receive Data Valid. Indicates that there is a receive frame in progress

and that the data present on the RXD signals is valid.

CPn+3_0

Table 6 1

CPn+3_1

Table 6 1

LVTTL

CRS

Carrier Sense. Indicates traffic is on the link. CRS is asserted when a

non-idle condition is detected on the receive data stream. CRS is

deasserted when an end of frame or idle condition is detected.

CPn+3_2

Table 6 1

LVTTL

RXD(4)

Receive Data

CPn+3_3

Table 6 1

LVTTL

RXD(5)

Receive Data

CPn+3_4

Table 6 1

LVTTL

RXD(6)

Receive Data

CPn+3_5

Table 6 1

LVTTL

RXD(7)

Receive Data (most significant bit)

CPn+3_6

Table 6 1

LVTTL

RX_ER

Receive Error Detected. Indicates that there has been an error

received in the receive frame.

TOTAL PINS

* n can be 0, 4, 8, or 12.

† Reference Table 6 for pin numbers for the actual cluster(s) you are configuring.

Table 10 Gigabit Ethernet (GMII/MII) Signals One Cluster Example (continued)

SIGNAL NAME*

PIN #†

TOTAL

TYPE

I/O

LABEL

SIGNAL DESCRIPTION

Freescale Semiconductor, Inc.

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