C5NPD0-DS datasheet(15/100 Pages) FREESCALE

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Revision History

V 04

Warning:

This icon and text indicate a procedure where the reader must take

precautions regarding laser light.

This icon and text indicate the possibility of electro-static discharge (ESD) in a procedure

that requires the reader to take the proper ESD precautions.

Revision History

Table 2 shows the revision history for this data sheet, providing a description of the

changes.

Table 2 C-5 Network Processor Data Sheet Revision History

REVISION DATE

CHANGE

PAGE NO.

March 10, 2000

First printing for the C-5 NP.

June 12, 2000

Chapter 2 contains the following revisions:

• LVTTL and LVPECL specifications have been added.

• Several of the tables listing pin configurations have had

their descriptions updated. Check each application’s

configuration table as required.

• CPn3+1 is RCLKN (5/25/00), not NC (3/10/00)

• Mechanism for EPROM signaling has changed.

• XPUHOT functionality is clarified

• QCPA is a NC (5/25/00), not Address Parity (3/10/00)

• The power and ground connections illustration has been

updated.

Chapter 3 contains the following revisions:

• Many values listed in individual timing diagrams and

specification tables have updated or corrected. Check each

specification table as required.

• Low speed serial interface timing specifications have been

added.

• PROM I/F timing specifications are changed

18 - 39

61 - 78

June 14, 2000

QMU timing specification for Tqdo has been changed from

2.2 to 1.5.

July 17, 2000

Updated BMU section to reflect change to external Pipeline

Architecture, Single Data Rate Synchronous DRAM.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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