C5NPD0-DS datasheet(63/100 Pages) FREESCALE

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JTAG Support

V 04

JTAG Support

The C-5 NP contains JTAG test logic compliant with the IEEE 1149.1 specification. All

required public instructions are implemented, as well as some optional instructions. This

section contains information regarding the pinout, instructions, identification codes, and

boundary scan cell types.

Pinout

The C-5 NP uses the standard JTAG pins including the optional test reset pin. Table 28

describes the pins and their functions. Note that pins for JTRSTX, JTDI, and JTMS require

external pullups on the board. These ports do not have internal pullups as required by the

1149.1 specification.

AB 1-29

AB1

CP3_0

AB9

CP5_1

AB17

CP4_5

AB25

CP2_4

AB2

CP3_1

AB10

CP5_2

AB18

CP4_4

AB26

CP2_3

AB3

CP3_2

AB11

CP5_3

AB19

CP4_3

AB27

CP2_2

AB4

CP3_3

AB12

CP5_4

AB20

CP4_2

AB28

CP2_1

AB5

CP3_4

AB13

CP5_5

AB21

CP4_1

AB29

CP2_0

AB6

CP3_5

AB14

CP5_6

AB22

CP4_0

AB7

CP3_6

AB15

JTDI

AB23

CP2_6

AB8

CP5_0

AB16

CP4_6

AB24

CP2_5

AC 1-29

AC1

VSS

AC9

VSS

AC17

VSS

AC25

VSS

AC2

CP1_0

AC10

CP1_4

AC18

CP0_5

AC26

CP0_1

AC3

VDD

AC11

VDD33

AC19

VDD

AC27

VDD

AC4

CP1_1

AC12

CP1_5

AC20

CP0_4

AC28

CP0_0

AC5

VSS

AC13

VSS

AC21

VSS

AC29

VSS

AC6

CP1_2

AC14

CP1_6

AC22

CP0_3

AC7

VDD

AC15

VDD

AC23

VDD33

AC8

CP1_3

AC16

CP0_6

AC24

CP0_2

Table 30 Signals Listed by Pin Number (continued)

FUNCTION

Freescale Semiconductor, Inc.

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