C5NPD0-DS datasheet(17/100 Pages) FREESCALE

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Documentation

The following table lists the C-5 and CST documentation set. Find the latest editions of

these documents for your installed CST version in the Support section of the C-Port

Corporation web site:

October 1, 2001

Chapter 2 contains the following revisions:

• LVTTL and LVPECL conform to the JEDEC

JESD8-BSpecification

• Table 3 changed to note LVPECL differential signal

• Table 10 LVPECL change

• Table 11 CPn_6 and CPn+1_6 changed

• Table 21 changed to reflect pin G14 used for signal MDQML

• Table 27 changed to reflect total number of NC pins for D0

• Table 28 changed to reflect G14 receiving signal MDQML

• C-Port web site support address added

Chapter 3 contains the following revisions

• Table 32 Storage / max junction temperatures added

• Table 34 LVPECL high and low voltage min / max added

• Table 36 Power dissipation, P

D min, max, typical changed

Chapter 4 contains the following revisions

• Added “Marking Codes”

• Added “Reflow” profile

September 9, 2002 Chapter 1 contains the following revisions:

• Table 4 contain revised TLU SRAM Configuration

specifications

Chapter 2 contains the following revisions:

• TLU SRAM Interface Signals: Table 24 and Table 25 changed

to reflect Memory Bank Selection

Chapter 3 contains the following revisions:

• Table 50, Table 51 and Table 53 contain revised timing

specifications

87 thru 90

Table 2 C-5 Network Processor Data Sheet Revision History

REVISION DATE

CHANGE

PAGE NO.

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C5NPD0-DS Datasheet(PDF) 17 Page - Freescale Semiconductor, Inc