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C5NPD0-DS Datasheet(PDF) 84 Page - Freescale Semiconductor, Inc |
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C5NPD0-DS Datasheet(HTML) 84 Page - Freescale Semiconductor, Inc |
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84 / 100 page  84 CHAPTER 3: ELECTRICAL SPECIFICATIONS C5NP PROM Interface Timing Specifications The PROM interface timing is shown in Figure 21 and described in Table 49. Figure 21 PROM Interface Timing Diagram Tbuf Bus Free Time Between a STOP and START Condition 1250 ns Cmax Capacitive load for each line of the bus 400 pF Table 48 Low Speed Serial Interface Timing Description (continued) (continued) SYMBOL PARAMETER MIN MAX UNIT SPCK Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 SPDI SPLD SPDO Tspc Tsplo Tspis Tspih Tspdo Table 49 PROM Interface Timing Description SYMBOL PARAMETER CLOCK MODE MIN TYP MAX UNIT Tspc SPCK Cycle Time 40.0 ns Tspis SPDI Setup 10.0 ns Tspih SPDI Hold 0.0 ns Tsplo SPLD Output 1X Tsc* * Tsc is the System Cycle Time. See Table 39 on page 74 Tsc + 3.0 ns 2X 2 x Tsc* 2 x Tsc + 3.0 ns Tspdo SPDO Output 1X Tsc* Tsc + 3.0 ns 2X 2 x Tsc* 2 x Tsc + 3.0 ns Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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