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C5NPD0-DS Datasheet(PDF) 74 Page - Freescale Semiconductor, Inc |
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C5NPD0-DS Datasheet(HTML) 74 Page - Freescale Semiconductor, Inc |
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74 / 100 page  74 CHAPTER 3: ELECTRICAL SPECIFICATIONS C5NP Unused clocks should be pulled to a known state (ground) through a resistor. If you are using a clock generator, disabling the output should not cause a tristate. If it does, then the line should be pulled down. CP Timing Specifications This section describes the timing for the following CP interfaces: • DS1/DS3 Ethernet Timing Description • 10/100 Ethernet Timing Description • Gigabit GMII/MII Ethernet Interface Timing Description • OC-3 Timing Description Table 39 System Clock Timing Description SYMBOL PARAMETER MIN TYP MAX UNIT COMMENT 1X CLK MODE 2X CLK MODE 1X CLK MODE 2X CLK MODE Tsc System Cycle Time 6.0 5.0 4.3 3.0 2.5 2.14 ns 166MHz core clock 200MHz core clock 233MHz core clock Tsh Sys Clk High Pulse 45 30 55 70 Duty cycle* Tsl Sys Clk Low Pulse 45 30 55 70 Duty cycle† Tcc0 CCLK0 Cycle Time 647.67 ns T1† Tcc1 CCLK1 Cycle Time 488.28 ns E1† Tcc2 CCLK2 Cycle Time 29.097 ns E3† Tcc3 CCLK3 Cycle Time 22.353 ns T3† Tcc4 CCLK4 Cycle Time 20.00 ns RMII† Tcc5 CCLK5 Cycle Time 9.412 ns Fibre Channel† Tcc6 CCLK6 Cycle Time 8.00 ns GMII† Tcc7 CCLK7 Cycle Time 6.43 ns OC-3† Tcch CCLKm High Time 40% 40% 60% 60% % cycle pulse is high Tccl CCLKm Low Time 40% 40% 60% 60% % cycle pulse is low * Pulse duty cycle measured at crossing voltage of SCLK/SCLKX † The frequencies specified for CCLK0 - CCLK7 allow full flexibility for the C-5 NP . Clock inputs associated with a specific protocol should be tied to ground when that protocol is not used by the C-5 NP . It is also possible to use one or more CCLKn inputs for other frequencies; contact your C-Port representative for more information. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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