C5NPD0-DS datasheet(48/100 Pages) FREESCALE

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CHAPTER 2: SIGNAL DESCRIPTIONS

C5NP

MA0 - MA11

H22, I22, H23, H24, I24, H25, H26,

I26, H27, H28, I28, H29

LVTTL

Address Outputs: A0-A11 are sampled during the

ACTIVE command and READ/WRITE to select one

location out of the memory array in the respective

bank. The address inputs also provide the

op-code during a LOAD MODE REGISTER

command

MBA0 - MBA1

G18, H19

LVTTL

Bank Address Outputs: BA0 and BA1 define which

bank the ACTIVE, READ, WRITE or PRECHARGE

command is being applied

MCLK

I16

Reserved

MCASX

J21

LVTTL

Command Outputs: MRASX, MCASX, MWEX and

MCSX define the command being entered.

NOTE: MCSX is considered part of the command

code.

MRASX

I20

LVTTL

Command Outputs: MRASX, MCASX, MWEX and

MCSX define the command being entered. MCSX

is considered part of the command code.

MWEX

J20

LVTTL

Command Outputs: MRASX, MCASX, MWEX and

MCSX define the command being entered. MCSX

is considered part of the command code.

MCSX

H20

LVTTL

Chip Select: MCSX enables (registered LOW) and

disables (registered HIGH) the command decoder.

All commands are masked when MCSX is

registered HIGH. MCSX provides the external bank

selection on systems with multiple banks. MCSX is

considered part of the command code.

MDQM

MDQML

H21

G14

LVTTL

Input/Output Mask: MDQM is an input mask

signal for write accesses and an output enable

signal for read accesses. Input data is masked

when MDQM is sampled HIGH during a WRITE

cycle. The output buffers are placed in a high Z

state (two-clock latency) when MDQM is sampled

HIGH during the READ cycle.

NOTE: MDQML is an identical copy of MDQM

used to drive the loading on SDRAM

configurations with 2 DQM pins.

Table 23 BMU SDRAM Interface Signals (continued)

SIGNAL NAME

PIN #

TOTAL

TYPE

I/O

SIGNAL DESCRIPTION

Freescale Semiconductor, Inc.

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C5NPD0-DS Datasheet(PDF) 48 Page - Freescale Semiconductor, Inc

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