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C5NPD0-DS Datasheet(PDF) 32 Page - Freescale Semiconductor, Inc

Part # C5NPD0-DS
Description  C-5 Network Processor Silicon Revision D0
PDF  100 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

C5NPD0-DS Datasheet(HTML) 32 Page - Freescale Semiconductor, Inc

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CHAPTER 2: SIGNAL DESCRIPTIONS
C5NP
DS1/T1 Framer Interface Configuration
Table 7 describes the serial framer interface signals. For each CP (0-15), you can
implement one serial Framer interface.
10/100 Ethernet (RMII) Configuration
Table 8 describes the 10/100BASE-T Ethernet Reduced Media Independent Interface
(RMII) signals. For each CP (0-15), you can implement one 10/100 Ethernet interface.
CP3_2
AB03
CP7_2
AA06
CP11_2
Z10
CP15_2
X03
CP3_3
AB04
CP7_3
AA08
CP11_3
Z11
CP15_3
X04
CP3_4
AB05
CP7_4
AA10
CP11_4
Z12
CP15_4
X05
CP3_5
AB06
CP7_5
AA12
CP11_5
Z13
CP15_5
X06
CP3_6
AB07
CP7_6
AA14
CP11_6
Z14
CP15_6
X07
Table 6 CP Physical Interface Signals and Pins (Grouped by Clusters) (continued)
CP CLUSTER 1
CP CLUSTER 2
CP CLUSTER 3
CP CLUSTER 4
SIGNAL
PIN #
SIGNAL
PIN #
SIGNAL
PIN #
SIGNAL
PIN #
Table 7 DS1/T1 Framer Interface Signals
SIGNAL NAME*
PIN #†
TOTAL
TYPE
I/O
LABEL
SIGNAL DESCRIPTION
CPn_0
Table 6
1
LVTTL
O
TCLK
Transmit Clock (1.544MHz)
CPn_1
Table 6
1
LVTTL
I
RCLK
Receive Clock (1.544MHz)
CPn_2
Table 6
1
LVTTL
O
TData
Transmit Data
CPn_3
Table 6
1
LVTTL
O
TFrame
Transmit Frame Synchronization
CPn_4
Table 6
1
LVTTL
I
RData
Receive Data
CPn_5
Table 6
1
LVTTL
I
RFrame
Receive Frame Synchronization
CPn_6
Table 6
1
nc
nc
nc
nc
TOTAL PINS
7
* n can be from 0 to 15. See Table 6.
† Reference Table 6 for pin numbers for the actual cluster(s) you are configuring.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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