C5NPD0-DS datasheet(98/100 Pages) FREESCALE

98 / 100 page

100

INDEX

C5NP

PCI 39

Power Supply 50

PROM Interface 41

QMU SRAM Interface 50

Serial Interface 40

Serial Port 41

Test 52

TLU SRAM Interface 49

SONET OC-12 Transceiver Interface Configuration 37

SONET OC-3 Transceiver Interface Configuration 37

Specifications

10/100 Ethernet Timing 76

AC Timing 72

BMU Timing 88

Clock Timing 73

CP Timing 75

DS1/DS3 Timing 75

Electrical 67

Executive Processor Timing 82

Fabric Processor Timing 86

Gigabit GMII Ethernet, TBI and MII Interface Timing

Specification 77

Low Speed Serial Interface Timing 84

MDIO Serial Interface Timing 83

Mechanical 93

OC-12 Timing 81

OC-3 Timing 79

PCI Timing 82

PROM Interface Timing 85

QMU Timing 91

TLU Timing 90

XP Timing 82

System Clock Timing Description 74

System Clock Timing Diagram 74

System Interfaces

Executive Processor 23

Table Lookup Unit 25

Test Signals 52

Test Signals, Miscellaneous, For JTAG, Scan, and Internal Test

Routines 53

Thermal Performance for C-5 Network Processor Heat Sink 72

Timing Outline

PROM Interface 43

TLU Signal Groups 90

TLU SRAM Interface Signals 49

TLU Timing Description 90

TLU Timing Diagram 90

TLU Timing Specifications 90

Transceiver Interface Configuration

SONET OC-12 37

SONET OC-3 37

Transmit and Receive Pin Combinations for Gigabit Ethernet and

FibreChannel 33

Using C-Port Electronic Documents 13

Utopia2/Utopia3 ATM Mode, C-5 Network Processor to Fabric Interface

Pin Mapping 45

Utopia2/Utopia3 PHY Mode, C-5 Network Processor to Fabric Interface

Pin Mapping 45

XP Timing Specifications 82

Freescale Semiconductor, Inc.

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C5NPD0-DS Datasheet(PDF) 98 Page - Freescale Semiconductor, Inc

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